Specifications
Intel
®
810E2 Chipset Platform
R
4 Design Guide
3.1.1
System Memory Routing Example ..............................................................47
3.4.2. System Memory Connectivity ......................................................................48
3.5. Display Cache Interface.................................................................................................49
3.5.1. Display Cache Solution Space.....................................................................49
3.6. Hub Interface .................................................................................................................51
3.6.1. Data Signals.................................................................................................51
3.6.2. Strobe Signals..............................................................................................52
3.6.3. HREF Generation/Distribution .....................................................................52
3.6.4. Compensation..............................................................................................52
3.7. Intel
®
ICH2 .....................................................................................................................54
3.7.1. Decoupling ...................................................................................................54
3.8. 1.8V/3.3V Power Sequencing ........................................................................................55
3.9. Power Plane Splits .........................................................................................................57
3.10. Thermal Design Power ..................................................................................................57
3.11. IDE Interface ..................................................................................................................57
3.11.1. Cabling ........................................................................................................58
3.12. Cable Detection for Ultra ATA/66 and Ultra ATA/100 ....................................................58
3.12.1. Combination Host-Side/Device-Side Cable Detection.................................58
3.12.2. Device-Side Cable Detection .......................................................................60
3.12.3. Primary IDE Connector Requirements ........................................................61
3.12.4. Secondary IDE Connector Requirements....................................................62
3.13. AC’97 .............................................................................................................................63
3.13.1. AC’97 Audio Codec Detect Circuit and Configuration Options ....................64
3.13.1.1. Valid Codec Configurations.............................................................68
3.13.2. SPKR Pin Considerations ............................................................................68
3.14. CNR ...............................................................................................................................69
3.15. USB................................................................................................................................69
3.15.1. Disabling the Native USB Interface of Intel
®
ICH2.......................................70
3.16. ISA .................................................................................................................................71
3.17. IOAPIC Design Recommendation .................................................................................71
3.18. SMBus/SMLink Interface ...............................................................................................71
3.19. PCI .................................................................................................................................73
3.20. RTC................................................................................................................................73
3.20.1. RTC Crystal .................................................................................................74
3.20.2. External Capacitors .....................................................................................75
3.20.3. RTC Layout Considerations.........................................................................75
3.20.4. RTC External Battery Connection................................................................75
3.20.5. RTC External RTCRST Circuit ....................................................................76
3.20.6. RTC Routing Guidelines ..............................................................................77
3.20.7. VBIAS DC Voltage and Noise Measurements.............................................77
3.20.8. Power-well Isolation Control ........................................................................77
3.21. LAN Layout Guidelines ..................................................................................................79
3.21.1. Intel
®
ICH2 – LAN Interconnect Guidelines .................................................80
3.21.1.1. Bus Topologies ...............................................................................80
3.21.1.2. Point-to-Point Interconnect..............................................................81
3.21.1.3. LOM/CNR Interconnect...................................................................81
3.21.1.4. Signal Routing and Layout ..............................................................82
3.21.1.5. Crosstalk Consideration ..................................................................83
3.21.1.6. Impedances.....................................................................................83
3.21.1.7. Line Termination .............................................................................83
3.21.2. General LAN Routing Guidelines and Considerations.................................83
3.21.2.1. General Trace Routing Considerations...........................................83