Specifications

Intel
®
810E2 Chipset Platform
R
Design Guide 37
2.2.10.1. VCCcore Decoupling Design
• Ten or more 4.7 µF capacitors in 1206 packages.
All capacitors should be placed within the PGA370 socket cavity and mounted on the primary side
of the motherboard. The capacitors are arranged to minimize the overall inductance between
VCC
CORE
/Vss power pins, as shown in the following figure.
• 8 ea (min) 1 µF 0612 package placed in the Intel
®
PGA370 socket cavity.
Figure 7. Capacitor Placement on the Motherboard
2.2.10.2. VTT Decoupling Design
For Itt = 3.0 A (max).
• Nineteen - 0.1 µF capacitors in 0603 packages placed within 200 mils of AGTL+ termination
R-packs, one capacitor for every two R-packs. These capacitors are shown on the outer exterior of
Figure 7. These are located on the motherboard.
2.2.10.3. VREF Decoupling Design
Four - 0.1 µF capacitors in 0603 package placed near V
REF
pins (within 500 mils).