Specifications

Intel
®
810E2 Chipset Platform
R
Design Guide 35
2.2.7. Connecting RESET# and RESET2# on a Flexible PGA370
Design
The 810E2 chipset platform designs that support both the Celeron processor and Pentium III processor
must route the AGTL+ reset signal from the chipset to two pins on the processor, as well as to the ITP
connector. This reset signal is connected to pins AH4 (RESET#) and X4 (RESET#) at the PGA370
socket (See the following figure).
Figure 6. RESET# Schematic for PGA370 Designs
ITP
Pin X4
Processor
Pin AH4
lenITP
VTT
Daisy chain
10 pF
91
Ω
lenCPUlenCS
91
Ω
cs_rtt_stub
Chipset
VTT
240 Ω
22 Ω
cpu_rtt_stub
reset_routing_370
cpu_rtt_stub
Parameter
lenCS
lenITP
lenCPU
cs_rtt_stub
CPU+rtt_stub
Minimum
0.5
1
0.5
0.5
0.5
Maximum
1.5
3
1.5
1.5
1.5
On legacy 810 chipset platforms (ones that only have support for Celeron processors), RESET# is
delivered only to pin X4. On flexible 810E chipset platforms (ones that have support for both the
Celeron processor and the Pentium
II processors) using a 370-pin socket, RESET# is delivered to both
pins X4 and AH4.
2.2.8. Reset Strapping Options
LMD26 on the 82810E GMCH is used as a strap at reset to determine whether the system board is
supporting a 370-pin socket or an SC242 connector:
LMD26: 0 (or floating) = 370-pin socket [leave as no connect]
1 = SC242 slot [pull-up to 3.3V through an (approximately) 8.2 kΩ pull-up
resistor]