Specifications

Intel

810E2 Chipset Platform

32 Design Guide

2.2.2.4. Additional Considerations

• Distribute VTT with a wide trace. A 0.050” minimum trace is recommended to minimize DC losses.

Route the V

TT trace to all components on the host bus. Be sure to include decoupling capacitors.

• The V

TT voltage should be 1.5V ± 3% for static conditions and 1.5 V ± 9% for worst case transient

condition.

• Place resistor divider pairs for V

REF

generation at the 82810E GMCH component. V

REF

is also

delivered to the processor.

2.2.3. Undershoot/Overshoot Requirements

Undershoot and overshoot specificaitons become more critical as the process technology for

microprocessors shrinks due to thinner gate oxide. Violating these undershoot and overshoot limits will

degrade the life expectancy of the processor.

2.2.4. BSEL[1:0] Implementation for PGA370 Designs

The Pentium III processor utilizes the BSEL1 pin to select either a 100 MHz or 133 MHz system bus

frequency setting from the CK810E clock synthesizer. While the BSEL0 signal is still connected to the

PGA370 socket, the Pentium III processor does not utilize it. Only the Celeron processor (CPUID=0665)

utilizes the BSEL0 signal. The Pentium III processors are 3.3 V tolerant for these signals, as are the

CK810E and GMCH. However, the Celeron processor requires 2.5V logic levels on the BSEL signals.

A new clock synthesizer, the CK810E, has been designed to support selections of 66 MHz, 100 MHz,

and 133 MHz. The REF input pin has been redefined to be a frequency selection strap (BSEL1) during

power-on and then becomes a 14 MHz reference clock output. This maintains pin compatibility with the

CK810 clock synthesizer. The following figure details the new BSEL[1:0] circuit design for Flexible

PGA370 designs. Note that BSEL[1:0] are now pulled up using 1 kΩ

ΩΩ

Ω resistors. The following figure

shows the 82810E GMCH and processor straps for selecting the system bus frequency.