Specifications
Intel
®
810E2 Chipset Platform
R
30 Design Guide
2.2.2.1. Motherboard Layout Rules for AGTL+ Signals
Minimizing Crosstalk
The following general rules will minimize the impact of crosstalk in the high-speed AGTL+ bus design:
• Maximize the space between traces. Maintain a minimum of 10 mils (assuming a 5 mil trace)
between trace edges wherever possible. It may be necessary to use tighter spacing when routing
between component pins. When traces have to be close and parallel to each other, minimize the
distance that they are close together, and maximize the distance between the sections when the
spacing restrictions relaxes.
• Avoid parallelism between signals on adjacent layers if there is no AC reference plane between
them. As a rule of thumb, route adjacent layers orthogonally.
• Since AGTL+ is a low signal swing technology, it is important to isolate AGTL+ signals from other
signals by at least 25 mils. This will avoid coupling from signals that have larger voltage swings
(e.g., 5V PCI).
• Select a board stack-up that minimizes the coupling between adjacent signals. Minimize the nominal
characteristic impedance within the AGTL+ specification. This can be done by minimizing the
height of the trace from its reference plane, which minimizes the crosstalk.
• Route AGTL+ address, data and control signals in separate groups to minimize crosstalk between
groups. Comply with the requirements pointed out in the Intergroup AGTL+ signals in the “Trace
Width:Space Guidelines” table.
• Minimize the dielectric used in the system. This makes the traces closer to their reference plane and
thus, reduces the crosstalk magnitude.
• Minimize the dielectric process variation used in the PCB fabrication.
• Minimize the cross sectional area of the traces. This can be done by narrower traces and/or by using
thinner copper, but the tradeoff for this smaller cross-sectional area is a higher trace resistivity that
can reduce the falling edge noise margin because of the I*R loss along the trace.
2.2.2.2. Motherboard Layout Rules for Non-AGTL+ (CMOS) Signals
Non-AGTL+ (CMOS) Signals
Route these signals on any layer or any combination of layers.