Specifications

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Intel

810E2 Chipset Platform

Design Guide 3

Contents

1. Introduction ................................................................................................................................ 13

1.1. About This Design Guide .............................................................................................. 13

1.1.1. References .................................................................................................. 17

1.2. System Overview........................................................................................................... 18

1.2.1. Graphics and Memory Controller Hub (GMCH) .......................................... 19

1.2.2. Intel



82801BA I/O Controller Hub 2 (ICH2) ............................................... 19

1.2.3. System Configurations ................................................................................ 20

1.3. Platform Initiatives ......................................................................................................... 21

1.3.1. Hub Interface............................................................................................... 21

1.3.2. Integrated LAN Controller............................................................................ 21

1.3.3. Ultra ATA/100 Support ................................................................................ 21

1.3.4. Expanded USB Support .............................................................................. 21

1.3.5. SMBus ........................................................................................................ 21

1.3.6. Interrupt Controller ...................................................................................... 21

1.3.7. Firmware Hub (FWH) Flash BIOS .............................................................. 22

1.3.8. AC’97 6-Channel Support ........................................................................... 22

1.3.9. Low Pin Count (LPC) Interface.................................................................... 24

2. PGA370 Processor Design Guidelines ...................................................................................... 25

2.1. Electrical Differences for Flexible PGA370 Designs ..................................................... 25

2.2. PGA370 Socket Definition Details................................................................................. 25

2.2.1. Layout Guidelines for Intel

Pentium

III Processors.................................. 27

2.2.2. Determine General Topology and Layout ................................................... 28

2.2.2.1. Motherboard Layout Rules for AGTL+ Signals............................... 30

2.2.2.2. Motherboard Layout Rules for Non-AGTL+ (CMOS) Signals......... 30

2.2.2.3. THRMDP and THRMDN................................................................. 31

2.2.2.4. Additional Considerations ............................................................... 32

2.2.3. Undershoot/Overshoot Requirements......................................................... 32

2.2.4. BSEL[1:0] Implementation for PGA370 Designs......................................... 32

2.2.5. CLKREF Circuit Implementation ................................................................. 34

2.2.6. Undershoot/Overshoot Requirements......................................................... 34

2.2.7. Connecting RESET# and RESET2# on a Flexible PGA370 Design........... 35

2.2.8. Reset Strapping Options ............................................................................. 35

2.2.8.1. Power-Up/Reset Strap Options ...................................................... 36

2.2.9. Voltage Regulation Differences................................................................... 36

2.2.10. Decoupling Guidelines for Flexible PGA370 Designs ................................. 36

2.2.10.1. VCCcore Decoupling Design.......................................................... 37

2.2.10.2. VTT Decoupling Design................................................................... 37

2.2.10.3. VREF Decoupling Design ................................................................ 37

2.2.11. Thermal/EMI Differences ............................................................................ 38

2.2.12. Debug Port Changes................................................................................... 38

2.2.13. PGA370 Socket Connector Strapping Option ............................................. 39

3. Layout and Routing Guidelines .................................................................................................. 41

3.1. General Recommendations........................................................................................... 41

3.2. Nominal Board Stackup................................................................................................. 41

3.1 Component Quadrant Layouts ...................................................................................... 42

3.3. Intel

810E2 Chipset Component Placement................................................................ 45

3.4. System Memory Layout Guidelines............................................................................... 46

3.4.1. System Memory Solution Space ................................................................. 46