Specifications

Intel
®
810E2 Chipset Platform
R
Design Guide 29
Figure 2. Topology for 370-Pin Socket Designs with Single-Ended Termination (SET)
370pin_set.vsd
82810E
GMCH
PGA370
Socket
L(1): Z
0
=60 Ω ±15%.
Vtt
56 Ω
L2
L3
L1
Table 5. Segment Descriptions and Lengths for Figure 2
1
Segment Description Min length (inches) Max length (inches)
L1 + L2 Intel
®
82810E GMCH to Rtt
Stub
1.90 4.50
L2 PGA370 Pin to Rtt stub 0.0 0.20
L3 Rtt Stub length 0.50 2.50
NOTES:
1. All AGTL+ bus signals should be referenced to the ground plane for the entire route. See Chapter 4.
• AGTL+ signals should be routed with trace lengths within the range specified for L1+L2 from the
processor pin to the chipset.
• Use an intragroup AGTL+ spacing to line width to dielectric thickness ratio of at least 2:1:1 for
microstrip geomety. If ε
r
= 4.5, this should limit coupling to 3.4%. For example, intragroup AGTL+
routing could use 10 mil spacing, 5 mil traces, and a 5 mil prepreg between the signal layer and the
plane it references (assuming a 4-layer motherboard design).
• The trace width is recommended to be 5 mils and not greater than 6 mils.
The following table contains the trace width: space ratios assumed for this topology. The crosstalk cases
considered in this guideline involve three types: Intragroup AGTL+, Intergroup AGTL+, and AGTL+ to
non-AGTL+. Intragroup AGTL+ crosstalk involves interference between AGTL+ signals within the
same group. Intergroup AGTL+ crosstalk involves interference from AGTL+ signals in a particular
group to AGTL+ signals in a different group. An example of AGTL+ to non-AGTL+ crosstalk is when
CMOS and AGTL+ signals interfere with each other.
Table 6. Trace Width:Space Guidelines
Crosstalk Type Trace Width:Space Ratios
Intragroup AGTL+ signals (same group AGTL+) 5:10 or 6:12
Intergroup AGTL+ signals (different group AGTL+) 5:15 or 6:18
AGTL+ to non-AGTL+ Processor Signals 5:20 or 6:24