Specifications

Intel
®
810E2 Chipset Platform
R
28 Design Guide
Table 3. Example T
FLT_MIN
Calculations for 133 MHz Bus
1
Driver Receiver Clk
Period
2
TCO_MAX TSU_MIN ClkSKEW ClkJITTER MADJ Recommended
TFLT_MIN
3
Processor GMCH 7.50 2.70 2.72 0.20 0.25 0.40 3.73
GMCH Processor 7.50 5.35 1.20 0.20 0.25 0.40 2.60
NOTES:
1. All times in nanoseconds.
2. BCLK period = 7.50 ns @ 133.33 MHz.
3. The flight times in this column include margin to account for the following phenomena that Intel has observed
when multiple bits are switching simultaneously. These multi-bit effects can adversely affect flight time and
signal quality and are sometimes not accounted for in simulation. Accordingly, maximum flight times depend on
the baseboard design and additional adjustment factors or margins are recommended.
• SSO push-out or pull-in.
•
Rising or falling edge rate degradation at the receiver caused by inductance in the current return path,
requiring extrapolation that causes additional delay.
•
Crosstalk on the PCB and internal to the package can cause variation in the signals.
There are additional effects that may not necessarily be covered by the multi-bit adjustment factor and
should be budgeted as appropriate to the baseboard design. Examples include:
•
The effective board propagation constant (S
EFF
), which is a function of:

Dielectric constant (ε
r
) of the PCB material.

The type of trace connecting the components (stripline or microstrip).

The length of the trace and the load of the components on the trace. Note that the board propagation
constant multiplied by the trace length is a component of the flight time but not necessarily equal to the
flight time.
Table 4. Example T
FLT_MIN Calculations (Frequency Independent)
1
Driver Receiver THOLD ClkSKEW TCO_MIN Recommended
TFLT_MIN
Processor 82810E GMCH 0.10 0.15 0.35 0.40
Intel
®
82810E
GMCH
Processor 1.0 0.15 0.35 0.23
NOTES:
1. All times in nanoseconds.
2.2.2. Determine General Topology and Layout
In the SET (Set Ended Termination) topology for the 370-pin socket (PGA370), the termination should
be placed close to the processor on the motherboard. There is no termination present at the chipset end of
the network. Due to the lack of termination, SET will exhibit much more ringback than the dual-
terminated topology. Extra care is required in SET simulations to make sure that the ringback
specifications are met under the worst case signal quality conditions. 810E2 chipset designs require all
AGTL+ signals to be terminated with a 56 Ω termination on the motherboard. To ensure processor signal
integrity requirements it is highly recommended that all system bus signal segments to be referenced
to the ground plane for the entire route (See Chapter 4 for details).