Specifications

Intel
®
810E2 Chipset Platform
R
Design Guide 27
2.2.1. Layout Guidelines for Intel
®
Pentium
®
III Processors
The following layout guide supports designs using Celeron processors and the Pentium III processor with
the 810E2 chipset. The solution covers system bus speeds of 66/100 MHz for the Celeron processor and
100/133 MHz for the Pentium III processors. The solution proposed in this segment requires the
motherboard design to terminate the system bus AGTL+ signals with a 56 Ω ± 5% Rtt. The Pentium III
processor must also be configured to 110 Ω internal Rtt.
Initial Timing Analysis
The table below lists the AGTL+ component timings of the processors and 82810E GMCH defined at the
pins. These timings are for reference only; obtain each processor’s specifications from its respective
processor datasheet and appropriate 810E2 chipset component specification.
Table 2. Intel
®
Pentium
®
III Processor and Intel
®
82810E GMCH AGTL+ Parameters for Example
Calculations
IC Parameters Intel
®
Pentium
®
III
processor core at
133 MHz System Bus
Intel
®
82810E
GMCH
Notes
Clock to Output maximum (T
CO_MAX
) 2.70 3.70 2
Clock to Output minimum (T
CO_MIN
) 0.20 0.95 2
Setup time (T
SU_MIN
) 1.20 2.72 2,3
Hold time (T
HOLD
) 0.80 0.10
NOTES:
1. All times in nanoseconds.
2. Numbers in table are for reference only. These timing parameters are subject to change. Check the
appropriate component documentation for valid timing parameter values.
3. T
SU_MIN
= 2.72 ns assumes the 82810E GMCH sees a minimum edge rate equal to 0.3 V/ns.
Table 3 provides an example AGTL+ initial maximum flight time and Table 4 is an example minimum
flight time calculation for a 133 MHz, uni-processor system using the Pentium III processor/ 810E2
chipset system bus. Note that assumed values for clock skew and clock jitter were used. Clock skew and
clock jitter values are dependent on the clock components and distribution method chosen for a
particular design and must be budgeted into the initial timing equations as appropriate for each
design.
Table 3 and Table 4 are derived assuming:
• CLK
SKEW = 0.20 ns (Note: Assumes clock driver pin-to-pin skew is reduced to 50 ps by tying two
host clock outputs together (“ganging”) at clock driver output pins, and the PCB clock routing skew
is 150 ps. System timing budget must assume 0.175 ns of clock driver skew if outputs are not tied
together and a clock driver that meets the CK810E Clock Synthesizer/ Driver Specification is being
used.)
• CLK
JITTER = 0.250 ns
See the appropriate 810E2 chipset documentation, and CK810E Clock Synthesizer/Driver Specification
for details on clock skew and jitter specifications. Exact details of host clock routing topology are
provided with the platform design guideline.