Specifications

Intel
®
810E2 Chipset Platform
R
26 Design Guide
Table 1. Platform Pin Definition Comparison for Single Processor Designs
Pin # Legacy
PGA370
Pin Name
Flexible
PGA370
Pin Name
Function Type Notes
A29 Reserved DEP7# Data bus ECC data AGTL+, I/O 2
A31 Reserved DEP3# Data bus ECC data AGTL+, I/O 2
A33 Reserved DEP2# Data bus ECC data AGTL+, I/O 2
AC1 Reserved A33# Additional AGTL+ address AGTL+, I/O 2
AC37 Reserved RSP# Response parity AGTL+, I 2
AF4 Reserved A35# Additional AGTL+ address AGTL+, I/O 2
AH20 Reserved VTT AGTL+ termination voltage Power
AH4 Reserved RESET# Processor reset (Intel
®
Pentium
®
III
processor)
AGTL+, I 3
AJ31 GND BSEL1 System bus frequency select CMOS, I/O 1
AK16 Reserved VTT AGTL+ termination voltage Power
AK24 Reserved AERR# Address parity error AGTL+, I/O 2
AL11 Reserved AP0# Address parity AGTL+, I/O 2
AL13 Reserved VTT AGTL+ termination voltage Power
AL21 Reserved VTT AGTL+ termination voltage Power
AM2 GND Reserved Reserved Reserved 1
AN11 Reserved VTT AGTL+ termination voltage Power
AN13 Reserved AP1# Address parity AGTL+, I/O 2
AN15 Reserved VTT AGTL+ termination voltage Power
AN23 Reserved RP# Request parity AGTL+, I/O
B36 Reserved BINIT# Bus initialization AGTL+, I/O 2
C29 Reserved DEP5# Data bus ECC data AGTL+, I/O 2
C31 Reserved DEP1# Data bus ECC data AGTL+, I/O 2
C33 Reserved DEP0# Data bus ECC data AGTL+, I/O 2
E29 Reserved DEP6# Data bus ECC data AGTL+, I/O 2
E31 Reserved DEP4# Data bus ECC data AGTL+, I/O 2
G35 Reserved VTT AGTL+ termination voltage Power
V4 Reserved BERR# Bus error AGTL+, I/O 2
W3 Reserved A34# Additional AGTL+ address AGTL+, I/O 2
X4 RESET# RESET2# Processor reset (Value processors) AGTL+, I 3
X6 Reserved A32# Additional AGTL+ address AGTL+, I/O 2
Y33 GND CLKREF 1.25V PLL reference Power 1
NOTES:
1. These signals were previously defined as ground (Vss) connections in legacy designs utilizing the PGA370
socket to provide termination for unused inputs. For new Flexible PGA370 designs, use the new signal
definitions. These new signal definitions are backwards compatible with the Celeron processor (PPGA).
2. While these signals are not used with 810E/810E2 chipset designs, they are available for chipsets that do
support these functions. Only the Pentium III processor offers these capabilities in the PGA370 platform.
3. The AGTL+ reset signal, RESET#, is delivered to pin X4 on Legacy PGA370 designs. On Flexible PGA370
designs it is delivered to X4 and AH4 pins. See Figure 2 for more details.