Specifications

Intel
®
810E2 Chipset Platform
R
Design Guide 21
1.3. Platform Initiatives
1.3.1. Hub Interface
As I/O speeds increase, the demand placed on the PCI bus by the I/O bridge has become significant.
With the addition of AC’97 and Ultra ATA/100, coupled with the existing USB, I/O requirements could
impact PCI bus performance. The 810E2 chipset’s hub interface architecture ensures that the I/O
subsystem (both PCI and the integrated I/O features such as IDE, AC’97, USB, etc.), receives adequate
bandwidth. By placing the I/O bridge on the hub interface (instead of PCI), the hub architecture ensures
that both the I/O functions integrated into the ICH2 and the PCI peripherals obtain the bandwidth
necessary for peak performance.
1.3.2. Integrated LAN Controller
The 810E2 chipset platform incorporates an ICH2 integrated LAN Controller. Its bus master capabilities
enable the component to process high-level commands and perform multiple operations; this lowers
processor utilization by off-loading communication tasks from the processor.
The ICH2 functions with several options of LAN connect components to target the desired market
segment. The 82562EH provides a HomePNA 1-Mbit/sec connection. The 82562ET provides a basic
Ethernet 10/100 connection. The 82562EM provides an Ethernet 10/100 connection with the added
flexibility of Alert on LAN.
1.3.3. Ultra ATA/100 Support
The 810E2 chipset platform incorporates the ICH2 IDE controller with two sets of interface signals
(primary and secondary) that can be independently enabled, tri-stated or driven low. The platform
supports Ultra ATA/100 for transfers up to 100 MB/sec, in addition to Ultra ATA/66 and Ultra ATA/33
modes.
1.3.4. Expanded USB Support
The 810E2 chipset platform contains two USB Host Controllers. Each Host Controller includes a root
hub with two separate USB ports each, for a total of 4 USB ports. The addition of a second USB Host
Controller expands the functionality of the platform.
1.3.5. SMBus
The ICH2 integrates a SMBus controller. The SMBus provides an interface for managing peripherals
such as serial presence detection (SPD) and thermal sensors. The slave interface allows an external
microcontroller to access system resources.
1.3.6. Interrupt Controller
The interrupt capabilities of the 810E2 chipset platform expand support for up to 8 PCI interrupt pins
and PCI 2.2 message-based interrupts. In addition, the ICH2 supports system bus interrupt delivery.