Specifications

Intel
®
810E2 Chipset Platform
R
Design Guide 19
1.2.1. Graphics and Memory Controller Hub (GMCH)
The GMCH provides the interconnect between the SDRAM and the rest of the system logic:
• 421 Mini BGA
• Integrated Graphics controller
• 230 MHz RAMDAC
• Support for the Celeron processor and Pentium III processor with a 66 MHz , 100 MHz, or
133 MHz system bus.
• 100 MHz SDRAM interface supporting 64 MB/256 MB/512 MB with 16Mb/64Mb/128Mb
SDRAM technology
• Optional 4 MB Display Cache
• Downstream hub interface for access to the ICH2
• TV-Out/Flat Panel Display support
1.2.2. Intel



82801BA I/O Controller Hub 2 (ICH2)
The I/O Controller Hub 2 provides the I/O subsystem with access to the rest of the system:
• Upstream hub interface for access to the GMCH
• PCI 2.2 interface with 6 PCI Req/Grant Pairs
• Bus Master IDE controller; supports Ultra ATA/100
• I/O APIC
• USB controller
• SMBus controller
• FWH interface
• LPC interface
• AC’97 2.1 interface
• Integrated System Management Controller
• Alert-on-LAN
• Interrupt controller
• Packaging / Power
 360 EBGA
 1.8 V core and 3.3 V standby