Specifications

Intel
®
810E2 Chipset Platform
R
Design Guide
183
Figure 98. Processor System Bus Valid Delay Timings
CLK
Signal
000762b
T
x
T
x
T
pw
V Valid Valid
T
x
T7, T11, T29 (Valid Delay)=
T
pw
T14, T15 (Pulse Wdith)
=
V
1.0V for GTL+ signal group; 1.25V for CMOS, APIC and JTAG signal groups
=
Figure 99. Processor System Bus Setup and Hold Timings
CLK
Signal
V Valid
T
s
T8, T12, T27 (Setup Time)=
T
h
T9, T13, T28 (Hold Time)=
V
1.0V for GTL+ signal group; 1.25V for CMOS, APIC and JTAG signal groups
=
T
h
T
s
Figure 100. Power-On Reset and Configuration Timings
T
a
BCLK
V
CC
, core,
V
REF
T
a
= T15 (PWRGOOD Inactive Pulse Width)
T
b
= T10 (RESET# Pulse Width)
T
b
PWRGOOD
RESET#
Vil, max
Vih, min