Specifications

Intel
®
810E2 Chipset Platform
R
182 Design Guide
Figure 97. BCLK Waveform
761a
2.0V
1.25V
0.5V
t
r
t
p
t
f
t
h
t
l
CLK
T
r
= T5 (Rise Time)
T
f
= T6 (Fall Time)
T
h
= T3 (High Time)
T
l
= T4 (Low Time)
T
p
= T1 (BLCK Period)
Table 52. Processor System Bus AC Guidelines (AGTL+ Signal Group) at the Processor
Pins
1, 2, 3, 4
T# Parameter Min Max Unit Figure Notes
T7: AGTL+ Output Valid Delay 0.30 4.43 ns Figure 98 5
T8: AGTL+ Input Setup Time 1.75 ns Figure 99 5, 6, 7, 8
T9: AGTL+ Input Hold Time 0.85 ns Figure 99 9
T10: RESET# Pulse Width 1.00 ms Figure
100
7, 10
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. These specifications are tested during manufacturing.
3. All AC timings for the AGTL+ signals are referenced to the BCLK rising edge at 1.25V at the processor pin. All
AGTL+ signal timings (compatibility signals, etc.) are referenced at 1.00V at the processor pins.
4. This specification applies to the processor operating with a 66 MHz or 100 MHz system bus.
5. Valid delay timings for these signals are specified into 25
Ω to 1.5V and with VREF at 1.0V.
6. A minimum of 3 clocks must be guaranteed between two active-to-inactive transitions of TRDY#.
7. RESET# can be asserted (active) asynchronously, but must be deasserted synchronously.
8. Specification is for a minimum 0.40V swing.
9. Specification is for a maximum 1.0V swing.
10. After Vcc
CORE
and BCLK become stable.