Specifications

Intel
®
810E2 Chipset Platform
R
Design Guide
181
8.1.2. System Bus AC Guidelines
Table 51 and Table 52 contain 66 MHz and 100 MHz system bus AC Guidelines defined at the
processor pins. For 133 MHz see the Intel

Pentium

III processor PGA 370 Socket datasheet.
Table 51 contains the BCLK guidelines and Table 52 contains the AGTL+ system bus guidelines.
Processor System Bus AC Specifications for the AGTL+ Signal Group at the processor pins for
100 MHz are equivalent to 66 MHz. The 66 MHz specification is documented in the processor datasheet.
Table 51. Flexible Motherboard Processor System Bus AC Guidelines (Clock) at the Processor
Pins
1,2,3
T# Parameter Min Nom Max Unit Figure Notes
System Bus Frequency 66.67
100.00
MHz
MHz
All processor core
frequencies
T1: BCLK Period 15.0
10.0
ns
ns
Figure 97
Figure 97
4, 5, 9 4, 6, 9
T2: BCLK Period Stability ±300
±250
ps
ps
Figure 97
Figure 97
5, 7, 8, 9 6, 7, 8, 9
T3: BCLK High Time 4.94
2.5
ns Figure 97
Figure 97
@>2.0V
5
@>2.0V
6
T4: BCLK Low Time 4.94
2.4
ns Figure 97
Figure 97
@<0.5V
5
@<0.5V
6
T5: BCLK Rise Time 0.34
0.38
1.5
1.36
ns
ns
Figure 97
Figure 97
(0.5V2.0V)
5, 11
(0.5V2.0V)
6, 11
T6: BCLK Fall Time 0.34
0.38
1.5
1.36
ns
ns
Figure 97
Figure 97
(2.0V0.5V)
5, 11
(2.0V0.5V)
6, 11
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
2. All AC timings for the AGTL+ signals are referenced to the BCLK rising edge at 1.25V at the processor core
pin. All AGTL+ signal timings (address bus, data bus, etc.) are referenced at 1.00V at the processor core pins.
3. All AC timings for the CMOS signals are referenced to the BCLK rising edge at 1.25V at the processor core
pin. All CMOS signal timings (compatibility signals, etc.) are referenced at 1.25V at the processor core pins.
4. The BCLK period allows a +0.5 ns tolerance for clock driver variation.
5. This specification applies to the processor when operating with a system bus frequency of 66 MHz.
6. This specification applies to the processor when operating with a system bus frequency of 100 MHz.
7. Due to the difficulty of accurately measuring clock jitter in a system, it is recommended that a clock driver be
used that is designed to meet the period stability specification into a test load of 10 to 20 pF. This should be
measured on the
rising edges of adjacent BCLKs crossing 1.25V at the processor core pin. The jitter
present must be accounted for as a component of BCLK timing skew between devices.
8. The clock driver’s closed loop jitter bandwidth must be set low to allow any PLL-based device to track the jitter
created by the clock driver. The –20 dB attenuation point, as measured into a 10 to 20 pF load, should be less
than 500 kHz. This specification may be ensured by design characterization and/or measured with a spectrum
analyzer.
9. The average period over a 1 uS period of time must be greater than the minimum specified period.