Specifications

Intel

810E2 Chipset Platform

18 Design Guide

1.2. System Overview

The 810E2 chipset enhances the performance of the first generation Integrated Graphics chipset designed

for the Intel

Celeron

processor and Intel

Pentium

III processor. The graphics accelerator architecture

consists of dedicated multi-media engines executing in parallel to deliver high performance 3D, 2D, and

motion compensation video capabilities. An integrated centralized memory arbiter allocates memory

bandwidth to multiple system agents to optimize system memory utilization. A new chipset component

interconnect, the hub interface, is designed into the 810E2 chipset to provide an efficient communication

channel between the memory controller hub and the I/O hub controller.

The 810E2 chipset architecture also enables a new security and manageability infrastructure through a

Firmware Hub Flash BIOS component.

An ACPI compliant 810E2 chipset platform can support the Full-on (S0), Stop Grant (S1), Suspend to

RAM (S3), Suspend to Disk (S4), and Soft-off (S5) power management states. Through the use of an

appropriate LAN device, the 810E2 chipset also supports wake-on-LAN

for remote administration and

troubleshooting.

The 810E2 chipset architecture removes the requirement for the ISA expansion bus that was traditionally

integrated into the I/O subsystem of PCIsets/AGPsets. This removes many of the conflicts experienced

when installing hardware and drivers into legacy ISA systems. The elimination of ISA provides true

plug-and-play for the 810E chipset platform. Traditionally, the ISA interface was used for audio and

modem devices. The addition of AC’97 allows the OEM to use software configurable AC’97 audio and

modem coder/decoders (codecs) instead of the traditional ISA devices.

The 810E2 chipset contains two core components:

• Intel

82810E Graphics and Memory Controller Hub (GMCH)

• Intel

82801BA I/O Controller Hub 2 (ICH2)

The GMCH integrates a 66/100/133 MHz, P6 family system bus controller, integrated 2D/3D graphics

accelerator, 100 MHz SDRAM controller and a high-speed hub interface for communication with the I/O

Controller Hub (ICH2). The ICH2 integrates an Ultra ATA/100 controller, 2 USB host controllers with a

total of 4 ports, LPC interface controller, FWH Flash BIOS interface controller, PCI interface controller,

AC’97 digital controller and a hub interface for communication with the GMCH.