Specifications

Intel
®
810E2 Chipset Platform
R
176 Design Guide
7.4. System Checklist
Checklist Items Recommendations
KEYLOCK# Pull up through 10-kΩ resistor to Vcc3_3.
PBTN_IN Connects to PBSwitch and PBin.
PWRLED Pull up through a 220-Ω resistor to Vcc5.
R_IRTX Signal IRTX after it is pulled down through 4.7-kΩ resistor to GND and passes
through 82-Ω resistor.
IRRX Pull up to 100-kΩ resistor to Vcc3_3.
When signal is input for SI/O decouple through 470-pF capacitor to GND
IRTX Pull down through 4.7 kΩ to GND.
Signal passes through 82-Ω resistor.
When signal is input to SI/O decouple through 470-pF capacitor to GND
FP_PD Decouple through a 470-pF capacitor to GND.
Pull up 470 Ω to Vcc5.
PWM1, PWM2 Pull up through a 4.7-kΩ resistor to Vcc3_3.
7.5. FWH Checklist
Checklist Items Recommendations
No floating inputs Unused FGPI pins must be tied to a valid logic level.
WPROT, TBLK_LCK Pull up through a 4.7-kΩ resistor to Vcc3_3.
R_VPP Pulled up to Vcc3_3 and decoupled with two 0.1-µF capacitors to
GND.
FGPI0_PD, FGPI1_PD, FGPI2_PD,
FPGI3_PD, FPGI4_PD, IC_PD
Pull down through a 8.2-kΩ resistor to GND.
FWH_ID1, FWH_ID2, FWH_ID3 Pull down to GND.
INIT# FWH INIT# must be connected to processor INIT#.
RST# FWH RST# must be connected to PCIRST#.
ID[3:0] For a system with only one FWH device, tie ID[3:0] to ground.