Specifications

Intel
®
810E2 Chipset Platform
R
172 Design Guide
7.2.16. Power
Checklist
Items
Recommendations
V_CPU_IO[1:0] The power pins should be connected to the proper power plane for the processor 's CMOS
Compatibility Signals. Use one 0.1 µF decoupling cap.
VccRTC No clear CMOS jumper on VccRTC. Use a jumper on RTCRST# or a GPI, or use a safemode
strapping for Clear CMOS
Vcc3.3 Requires six 0.1 µF decoupling capacitors
VccSus3.3 Requires one 0.1 µF decoupling capacitor.
Vcc1.8 Requires two 0.1 µF decoupling capacitors.
VccSus1.8 Requires one 0.1 µF decoupling capacitor.
V5_REF SUS Requires one 0.1 µF decoupling capacitor.
V5REF_SUS only affects 5V-tolerance for USB OC:[3:0]# pins and can be connected to either
VccSUS3_3 or 5V_Always/5V_AUX if 5V tolerance on these OC:[3:0]# is not needed. If 5V
tolerance on OC:[3:0]# is needed then V5REF_SUS USB must be connected to
5V_Always/5V_AUX which remains powered during S5.
5V_REF 5VREF is the reference voltage for 5V tolerant inputs in the ICH2. Tie to pins VREF[2:1].
5VREF must power up before or simultaneous to Vcc3_3. It must power down after or
simultaneous to Vcc3_3. Refer to the figure below for an example circuit schematic that may
be used to ensure the proper 5VREF sequencing.
Figure 94. V5REF Circuitry
Vcc Supply
(3.3V)
5V Supply
To SystemV
REF To System
1 K Ω
1.0 uF
vref_circuit