Specifications

Intel
®
810E2 Chipset Platform
R
168 Design Guide
7.2.9. Power Management
Checklist
Items
Recommendations
THRM# Connect to temperature Sensor. Pull-up if not used.
SLP_S3#
SLP_S5#
No pull-up/down resistors needed. Signals driven by ICH2.
PWROK This signal should be connected to power monitoring logic, and should go high no sooner than
10 ms after both Vcc3_3 and Vcc1_8 have reached their nominal voltages
PWRBTN# This signal has an integrated pull-up of 24K.
RI# RI# does not have an internal pull-up. Recommend an 8.2 kΩ pull-up resistor to Resume well.
If this signal is enabled as a wake event, it is important to keep this signal powered during the
power loss event. If this signal goes low (active), when power returns, the RI_STS bit will be
set and the system will interpret that as a wake event.
RSMRST# Connect to power monitoring logic, and should go high no sooner than 10 ms after both
VccSUS3_3 and VccSus1_8 have reached their nominal voltages. Requires weak pull-down.
Also requires well isolation control as directed in section 3.20.8
7.2.10. Processor Signals
Checklist
Items
Recommendations
A20M#,
CPUSLP#,
IGNNE#, INIT#,
INTR, NMI,
SMI#, STPCLK#
Internal circuitry has been added to the ICH2, external pull-up resistors are not needed.
FERR# Requires Weak external pull-up resistor to VCC
CMOS
.
RCIN#
A20GATE
Pull-up signals to VCC3.3 through a 10 kΩ resistor.
CPUPWRGD Connect to the processor’s CPUPWRGD input. Requires weak external pull-up resistor.