Specifications

Intel
®
810E2 Chipset Platform
R
166 Design Guide
Checklist
Items
Recommendations
PIRQ[G:F]#/
GPIO[4:3]
These signals require a pull-up resistor. Recommend a 2.7 kΩ pull-up resistor to VCC5 or
8.2 k
Ω to VCC3.3.
In Non-APIC Mode the PIRQx# signals can be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12,
14 or 15 as described in the Interrupt Steering section. Each PIRQx# line has a separate
Route Control Register.
In APIC mode, these signals are connected to the internal I/O APIC in the following fashion:
PIRQ[E]# is connected to IRQ20, PIRQ[F]# to IRQ21, PIRQ[G]# to IRQ22, and PIRQ[H]# to
IRQ23. This frees the ISA interrupts.
PIRQ[H]#
PIRQ[E]#
These signals require a pull-up resistor. Recommend a 2.7 kΩ pull-up resistor to VCC5 or
8.2 k
Ω to VCC3.3.
Since PIRQ[H]# and PIRQ[E]# are used internally for LAN and USB controllers, they cannot
be used as GPIO(s) pin.
APIC
• Intel Pentium
®
4 processor based systems:
 These processors do not have APIC pins so all platforms using this processor should
both tie APICCLK to ground and tie APICD:[1:0] to ground via a 1k-10k pull-down
resistor.
• Non- Pentium 4 processor based systems:
 If the APIC is used: 150Ω pull-up resistors on APICD[1:0]
 Connect APICCLK to CK133 with a 20-33Ω series termination resistor.
• If the APIC is not used on up systems:
 The APICCLK can either be tied to GND or connected to CK133, but not left floating.
 Pull APICD[1:0] to GND through 10kΩ pull-down resistors.
7.2.7. GPIO Checklist
Checklist Items Recommendations
All Ensure ALL unconnected signals are OUTPUTS ONLY!
GPIO[7:0] These pins are in the Main Power Well. Pull-ups must use the VCC3.3 plane. Unused
core well inputs must either be pulled up to VCC3.3 or pulled down. Inputs must not be
allowed to float. These signals are 5V tolerant.
GPIO[1:0] can be used as REQ[A:B]#. GPIO[1] can also used as PCI REQ[5]#.
[13:11], GPIO[8] These pins are in the Resume Power Well. Pull-ups must use the VCCSUS3.3 plane.
These are the only GPI signals in the resume well with associated status bits in the
GPE1_STS register. Unused
resume well inputs must be pulled up to VCCSUS3.3. These
signals are not 5V tolerant.
These are the only GPIs that can be used as ACPI compliant wake events.
GPIO[23:16] Fixed as output only. Can be left NC. In Main Power Well. GPIO22 is open drain.
GPIO[24,25,27,28] These I/O pins can be NC. These pins are in the resume power well.