Specifications

Intel
®
810E2 Chipset Platform
R
164 Design Guide
Checklist
Items
Recommendations Comments
5 Max mismatch between the length of a clock trace and the
length of any data trace is 0.5 inches (clock must be longest
trace)
To meet timing and signal
quality requirements.
6 Maintain constant symmetry and spacing between the traces
within a differential pair out of the LAN phy.
To meet timing and signal
quality requirements.
7 Keep the total length of each differential pair under 4 inches. Issues found with traces
longer than 4 inches : IEEE
phy conformance failures,
excessive EMI and or
degraded receive BER.
8 Do not route the transmit differential traces closer than
100 mils to the receive differential traces.
To minimize crosstalk.
9
Distance between differential traces and any other signal line
is 100 mils. (300 mils recommended)
To minimize crosstalk.
10 Route 5 mils on 7 mils for differential pairs (out of LAN phy) To meet timing and signal
quality requirements.
11 Differential trace impedance should be controlled to be
~100
Ω.
To meet timing and signal
quality requirements.
12 For high-speed signals, the number of corners and vias
should be kept to a minimum. If a 90 degree bend is required,
it is recommended to use two 45 degree bends.
To meet timing and signal
quality requirements.
13 Traces should be routed away from board edges by a
distance greater than the trace height above the ground
plane.
This allows the field around
the trace to couple more
easily to the ground plane
rather than to adjacent wires
or boards.
14 Do not route traces and vias under crystals or oscillators. This will prevent coupling to
or from the clock.
15 Trace width to height ratio above the ground plane should be
between 1:1 and 3:1.
To control trace EMI
radiation.
16 Traces between decoupling and I/O filter capacitors should be
as short and wide as practical.
Long and thin lines are
more inductive and would
reduce the intended effect
of decoupling capacitors.
17 Vias to decoupling capacitors should be sufficiently large in
diameter.
To decrease series
inductance.
18 Avoid routing high-speed LAN* or Phoneline traces near other
high-frequency signals associated with a video controller,
cache controller, processor, or other similar devices.
To minimize crosstalk.
19 Isolate I/O signals from high speed signals. To minimize crosstalk.
20 Place the 82562ET/EM part more than 1.5 inches away from
any board edge.
This minimizes the potential
for EMI radiation problems.
21 Place at least one bulk capacitor (4.7 µF or greater) on each
side of the 82562ET/EM.
Research and development
has shown that this is a
robust design requirement.
22 Place decoupling caps (0.1 µF) as close to the 82562ET/EM
as possible.