Specifications

Intel
®
810E2 Chipset Platform
R
162 Design Guide
Checklist Line Items Comments
LMD[27:31]
Reset strapping
options:
Strapping options: For a “1”, use a 10 kΩ (approximate) pull-up resistor to 3.3V; a “0” is
default (due to internal pull-down resistors).
LMD13: 0= LMD29 determines host bus frequency
1= host bus frequency is 133 MHz
LMD31: 0 = Normal operation
1 = XOR TREE for testing purposes
LMD30: 0 = Normal operation
1 = Tri-state mode for testing purposes (will tri-state all signals)
LMD29: 0 = System bus frequency = 66 MHz
1 = System bus frequency = 100 MHz
LMD28: The value on LMD28 sampled at the rising edge of CPURST#
reflects if the IOQD (In-Order Queue Depth) is set to 1 or 4.
0 = IOQD = 4
1 = IOQD = 1
LMD27: PGA370: Connect to V
CORE
DET
on the processor (pin E21) through a 10 kΩ
series resistor for the Celeron processor and Pentium
II
processor
For the Celeron processor and Pentium III processor, LMD27
should not be pulled up.
SC242: No Connect
HCOMP Option 1—RCOMP Method: Tie the HCOMP pin to a 40 Ω 1% or 2% (or 39 Ω 1%) pull-up
resistor to 1.8V via a 10 mil wide, very short (~0.5”) trace.
Option 2—ZCOMP Method: The HCOMP pin must be tied to a 10 mil trace that is AT
LEAST 18” long. This trace must be un-terminated and care should be taken when routing
the signal to avoid crosstalk (1520 mil separation between this signal and any adjacent
signals is recommended). This signal may not cross power plane splits.
Table 47. System Memory Checklist
Checklist Line Items Recommendations
Pin 147 Connect to Ground (since Intel
®
810E2 chipset does not support registered DIMMs).
WP (Pin 81 on the
DIMMs)
Add a 4.7 kΩ pull-up resistor to 3.3V. This is a recommendation to write-protect the DIMM’s
EEPROM.
MAA[7:4], MAB[7:4] Add 10 Ω series resistors to the MAA[7:4], MAB[7:4] as close as possible to GMCH for
signal integrity.
Table 48. Display Cache Checklist
Checklist Line Items Recommendations
CKE 4.7 kΩ pull-up resistor to VCC3.