Specifications

Intel
®
810E2 Chipset Platform
R
160 Design Guide
Table 45. Miscellaneous Checklist for 370-Pin Socket Processors
Processor Pin I/O Recommendations
BCLK I Connect to clock generator / 22–33 Ω series resistor (though OEM needs to simulate
based on driver characteristics). To reduce pin-to-pin skew, tie host clock outputs
together at the clock driver then route to the GMCH and processor.
BSEL0 I/O Case 1, 66/100/133 MHz support: 1 kΩ pull-up resistor to 3.3V, connect to CK810E
SEL0 input, connect to GMCH LMD29 pin via 10 k
Ω series resistor.
Case 2, 100/133 MHz support: 1 kΩ pull-up resistor to 3.3V, connect to PWRGOOD
logic such that a logic low on BSEL0 negates PWRGOOD.
BSEL1 I/O 1 kΩ pull-up resistor to 3.3V, connect to CK810E REF pin via 10 kΩ series resistor,
connect to GMCH LMD13 pin via 10 k
Ω series resistor.
CLKREF I Connect to divider on VCC_2.5 or VCC_3.3 to create 1.25V reference with a 4.7 µF
decoupling capacitor. Resistor divider must be created from 1% tolerance resistors.
Do
not use VTT as source voltage for this reference!
CPUPRES# Tie to ground, leave as No Connect, or could be connected to PWRGOOD logic to gate
system from powering on if no processor is present. If used, 1 k
Ω–10 kΩ pull-up resistor
to any voltage.
EDGCTRL I 51 Ω ±5% pull-up resistor to VCC
CORE
.
PICCLK I Connect to clock generator / 22–33 Ω series resistor (though OEM needs to simulate
based on driver characteristics).
PLL1, PLL2 I Low pass filter on VCC
CORE
provided on motherboard. Typically a 4.7 uH inductor in
series with VCC
CORE
is connected to PLL1 then through a series 33 µF capacitor to
PLL2.
RTTCTRL5
(S35)
110 Ω ±1% pull-down resistor to ground.
SLEWCTRL
(E27)
110 Ω ±1% pull-down resistor to ground.
THERMDN O No Connect if not used; otherwise connect to thermal sensor using vendor guidelines.
THERMDP I No Connect if not used; otherwise connect to thermal sensor using vendor guidelines.
VCC_1.5 I Connected to same voltage source as V
TT
. Must have some high and low frequency
decoupling.
VCC_2.5 I Connected to 2.5V voltage source. Should have some high and low frequency
decoupling.
VCC
CMOS
O Used as pull-up voltage source for CMOS signals between processor and chipset and for
TAP signals between processor and ITP. Must have some decoupling (HF/ LF) present.
VCC
CORE
I 10 ea (min) 4.7 µF in 1206 package all placed within the PGA370 socket cavity.
8 ea (min) 1 µF in 0612 package placed in the PGA370 socket cavity.
VCORE
DET
(E21)
O 220 Ω pull-up resistor to 3.3V, connect to GMCH LMD27 pin via 10 kΩ series resistor for
the Celeron
®
processor and Pentium
®
II processor.
For the Celeron processor and
Pentium
®
III processor VCOREdet must float.
VID[3:0] O Connect to on-board VR or VRM. For on-board VR, 10 kΩ pull-up resistor to power-
solution compatible voltage required (usually pulled up to input voltage of the VR). Some
of these solutions have internal pull-ups. Optional override (jumpers, ASIC, etc.) could be
used. May also connect to system monitoring device.
VID[4] N/A Connect regulator controller pin to ground (not on processor).