Specifications

Intel

810E2 Chipset Platform

Design Guide

153

If one of these signals goes high while one of its associated power planes is active and the other is not, a

leakage path will exist between the active and inactive power wells. This could result in high, possibly

damaging, internal currents.

6.4.3. 3.3V / V5REF Sequencing

V5REF is the reference voltage for 5V tolerance on inputs to the ICH2. V5REF must be powered up

before Vcc3_3, or after Vcc3_3 within .7V. Also, V5REF must power down after Vcc3_3, or before

Vcc3_3 within .7V. The rule must be followed in order to ensure the safety of the ICH2. If the rule is

violated, internal diodes will attempt to draw power sufficient to damage the diodes from the Vcc3_3

rail. Figure 87 shows a sample implementation of how to satisfy the V5REF/3.3V sequencing rule.

This rule also applies to the stand-by rails. However, in most platforms the VccSus3_3 rail is derived

from the VccSus5 and therefore, the VccSus3_3 rail will always come up after the VccSus5 rail. As a

result, V5REF_Sus will always be powered up before VccSus3_3. In platforms that do not derive the

VccSus3_3 rail from the VccSus5 rail, this rule must be comprehended in the platform design.

As an additional consideration, during suspend, the only signals that are 5V tolerant capable are USB

OC:[3:0]#. If these signals are not needed during suspend, V5REF_SUS can be connected to either

VccSus3_3 or 5V_Always/5V_AUX. If OC:[3:0]# is needed during suspend and 5V tolerance is

required then V5REF_SUS should be connected to 5V_Always/5V_AUX, but if 5V tolerance is not

needed in suspend, then V5REF_SUS can be connected to either VccSus3_3 or 5V_Always/5V_AUX

rails.

Figure 90. Example 3.3V/V5REF Sequencing Circuitry

5VREF_Seq_Circuit

Vcc Supply

(3.3V)

To System

VREF

5V Supply

1 K

Ω

1 uF