Specifications

Intel

810E2 Chipset Platform

152 Design Guide

6.4.2. 1.8V / 3.3V Power Sequencing

The ICH2 has two pairs of associated 1.8V and 3.3V supplies. These are (Vcc1_8, Vcc3_3) and

(VccSus1_8, VccSus3_3). These pairs are assumed to power up and power down together. The

difference between the two associated supplies must never be greater than 2.0V. The 1.8V supply

may come up before the 3.3V supply without violating this rule (though this is generally not practical in a

desktop environment, since the 1.8V supply is typically derived from the 3.3V supply by means of a

linear regulator).

One serious consequence of violation of this "2V Rule" is electrical overstress of oxide layers, resulting

in component damage.

The majority of the ICH2 I/O buffers are driven by the 3.3V supplies, but are controlled by logic that is

supply comes up first. In this case the I/O buffers will be in an undefined state until the 1.8V logic is

powered up. Some signals that are defined as "Input-only" actually have output buffers that are normally

disabled; the ICH2 may unexpectedly drive these signals if the 3.3V supply is active while the 1.8V

supply is not.

The figure below shows an example power-on sequencing circuit that ensures the “2V Rule” is obeyed.

This circuit uses a NPN (Q2) and PNP (Q1) transistor to ensure the 1.8V supply tracks the 3.3V supply.

The NPN transistor controls the current through PNP from the 3.3V supply into the 1.8V power plane by

varying the voltage at the base of the PNP transistor. By connecting the emitter of the NPN transistor to

the 1.8V plane, current will not flow from the 3.3V supply into 1.8V plane when the 1.8V plane reaches

1.8V.

Figure 89. Example 1.8V/3.3V Power Sequencing Circuit

PNP

NPN

220

470

+3.3V

+1.8V

When analyzing systems that may be "marginally compliant" to the 2V Rule, please pay close attention

to the behavior of the ICH2's RSMRST# and PWROK signals, since these signals control internal

isolation logic between the various power planes:

• RSMRST# controls isolation between the RTC well and the Resume wells.

• PWROK controls isolation between the Resume wells and Main wells