Specifications

Intel
®
810E2 Chipset Platform
R
Design Guide
147
Figure 87. S0-S5-S0 Transition
DRAM active
DRAM in STR (CKE low) DRAM active
Clocks valid Clocks invalid Clocks valid
t16t15
t9
t22
t8
t26
t25
t23t21
t17
t13
t12
t11t20
t19
t7t18
t24
Vcc3.3sus
RSMRST#
STPCLK#
Stop grant cycle
CPUSLP#
Go_C3 from ICH
Ack_C3 from GMCH
DRAM
SUS_STAT#
PCIRST#
Cycle 1 from GMCH
Cycle 1 from ICH2
Cycle 2 from GMCH
Cycle 2 from ICH2
CPURST#
SLP_S3#
SLP_S5#
PWROK
Vcc3.3core
Clocks
Freq straps
Wake event
pwr_S0-S5-S0_trans