Specifications

Intel
®
810E2 Chipset Platform
R
Design Guide
145
Figure 85. G3-S0 Transistion
Clocks invalid Clocks valid
t17
t16t15
t14
t13
t12
t10
t11
t9
t8
t7
t6
t5
t4
t3t2
t1
Vcc3.3sus
RSMRST#
SLP_S3#
SLP_S5#
SUS_STAT#
Vcc3.3core
CPUSLP#
PWROK
Clocks
PCIRST#
Cycle 1 from GMCH
Cycle 1 from ICH2
Cycle 2 from GMCH
Cycle 2 from ICH2
STPCLK#
Freq straps
CPURST#
pwr_G3-S0_trans