Specifications

Intel
®
810E2 Chipset Platform
R
144 Design Guide
Figure 84. Power Delivery Map
Intel
®
810E2 Chipset Universal
Socket 370 Platform
Power Map
VRM8.5
Proces sor
Fan
-12 V
Serial xceivers-5: 5 V ± 0.25 V
30 mA S0, S1
Serial xceivers-12: 12 V ± 1.2 V
22 mA S0, S1
Serial xceivers-N12: -12 V ± 1.2 V
28 mA S0, S1
Serial ports
Intel
®
810E2 chipset
VTT regulator
Display cache: 3.3 V ± 0.3 V
960 mA S0, S1
CK815-3.3: 3.3 V ± 0.165 V
280 mA S0, S1
CK815-2.5: 2.5 V ± 0.125 V
100 mA S0, S1
CLK
2.5 V regulator
1.8 V regulator
AC'97
3.3 VSB regulator
ATX P/S
with 720 mA
5 VSB
± 5%
12 V
± 5%
3.3 V
± 5%
5 V
± 5%
-12 V
± 10%
LPC super I/O: 3.3V ±0.3V
50 mA S0, S1
PS/2 keyboard/mouse 5 V ± 0.5 V
1 A S0, S1
Super I/O
2 DIMM slots: 3.3 VSB ± 0.3 V
7.2 A S0, S1; 96 mA S3
(3) PCI 3.3 Vaux: 3.3 VSB ± 0.3 V
1.125 A S0, S1; 60 mA S3, S5
82559 LAN down 3.3 VSB ± 0.3 V
195 mA S0,S1; 120 mA S3, S5
PCI
3V_DUAL
GMCH: 3.3 VSB ± 0.165 V
110 mA S3, S5
GMCH core: 1.8 V ± 3%
1.40 A S0, S1
GMCH: 3.3 V ± 0.165 V
1.40 A S0, S1
FWH core: 3.3 V ± 0.3 V
67 mA S0, S1
ICH2 resume: 3.3 VSB ± 0.3 V
1.5 mA S0, S1; 300 µA S3, S5
+0.1V, -0.2V 5mA S0, 2mA S1
ICH2 core: 3.3 V ± 0.3 V
300 mA S0, S1
ICH2 hub I/O: 1.8 V ± 0.09 V
55 mA S0, S1
pwr_del_map
AC'97 3.3 VSB: 3.3 VSB ± 0.165 V
1.0A S0, S1; 375 mA S3, S5
AC'97 12V: 12 V ± 0.6 V
500 mA S0, S1
AC'97 -12 V: -12 V ± 1.2 V
100 mA S0, S1
AC'97 5 V: 5 V ± 0.25 V
1.00 A S0,S1
AC'97 5 VSB: 5 VSB ± 0.25 V
500 mA S0, S1, S3, S5
AC'97 3.3 V: 3.3 V ± 0.165 V
1.00 A S0,S1
Notes:
Shaded regulators / components are ON in S3 and S5.
KB / mouse will not support STR.
Total max. power dissipation for GMCH = 4 W .
Total max. power dissipation for AC'97 = 15 W .
VDDQ regulator
GMCH VDDQ
2.3 A S0, S1
3V Dual
Switch
5V Dual
Switch
5V_DUAL
VCC3.3 V: 3.3V ±0.165V
15 mA S0, S1
VTT: 1.5V
1
2.7A S0, S1
VTT: 1.25V
1
2.7A S0, S1
Core: VCC_VID: 1.75V
1
22.0 A S0, S1
Core: VCC_VID: 1.5V
1
28.5 A S0, S1
1 Refer to processor datasheet for
voltage tolerance specifications
USB cable power: 5 V ± 0.25 V
2 A S0, S1; 1 mA S3, S5
ICH2 RTC: 3.3 VSB ± 0.3 V
5 µA S0, S1, S3, S5
ICH2 resume: 1.8 VSB
1.8mA S3, S5
250mA S0, S1
ICH2 CMOS: 1.5V ± 0.15
1.5V regulator
1.8 VSB regulator
6.1. Thermal Design Power
Thermal Design power (TDP) is defined as the estimated maximum possible expected power generated
in a component by a realistic application. It is based on extrapolations in both hardware and software
technology over the life of the product. It does not represent the expected power generated by a power
virus.
The TDP for the GMCH component is 4.0 W.
The TDP for the ICH2 is 1.5 W.
6.1.1. Power Sequencing
This section shows the timings between various signals during different power state transitions.