Specifications

Intel
®
810E2 Chipset Platform
R
140 Design Guide
5.5. Clock Power Decoupling Guidelines
Several general layout guidelines should be followed when laying out the power planes for the CK810E
clock generator.
• Isolate power planes to the each of the clock groups.
• Place local decoupling as close to power pins as possible and connect with short, wide traces and
copper.
• Connect pins to appropriate power plane with power vias (larger than signal vias).
• Bulk decoupling should be connected to plane with 2 or more power vias.
• Minimize clock signal routing over plane splits.
• Do not route any signals underneath the clock generator on the component side of the board.
• An example signal via is a 14 mil finished hole with a 24–26 mil path. An example power via is an
18 mil finished hole with a 33–38 mil path. For large decoupling or power planes with large current
transients it is recommended to use a larger power via.
An example of clock power layout is presented in the following figure.