Specifications

Intel
®
810E2 Chipset Platform
R
Design Guide
137
Table 39. Layout Dimensions
Group Receiver Resistor Cap Topology A B C D
MCLK DIMM
22
Ω N/A Layout 1 0.5” X N/A N/A
Processor
Intel
®
Pentium
®
III
FC-PGA
Processor
100/133 MHz
Segment C =>
Pentium III FC-
PGA Processor
Segment D =>
GMCH
33
Ω N/A Layout 5 0.1” 0.5” X+4.8" X+7.1”
Processor
Intel
®
Celeron
®
Processor
66/100 MHz
Segment C =>
Celeron Processor
Socket
Segment D =>
GMCH
33
Ω N/A Layout 5 0.1” 0.5” X+5.4" X+7.1”
DCLK GMCH
33
Ω 22 pF Layout 3 0.5” X+3.2” 0.5” N/A
3V66 GMCH
22
Ω 18 pF Layout 3 0.5” X+1.4” 0.5” N/A
3V66 ICH2
22
Ω 18 pF Layout 3 0.5” X+1.4” 0.5” N/A
PCI PCI device
33
Ω N/A Layout 1 0.5” X+3.0” to
X+9.3”
N/A N/A
PCI PCI socket
33
Ω N/A Layout 4 0.5” X+0.0” to
X+6.0”
N/A N/A
PCI ICH2
33
Ω N/A Layout 1 0.5” X+4.4” N/A N/A
TCLK SDRAM
22
Ω N/A Layout 6 0.5” 1.5” to 2.5” 0.75” to
1.25”
N/A
OCLK/RCLK GMCH
33
Ω N/A Layout 1 0.5” 3.25” to
3.75”
N/A N/A
APIC PPGA
33
Ω N/A Layout 4 0.5” Y N/A N/A
APIC ICH2
33
Ω N/A Layout 1 0.5” Y+2.4” N/A N/A
NOTES:
1. W, X, Y and Z trace lengths are arbitrary. Below are some suggested values:
X=5.0", Y=4.2".
The following figure shows the different topologies used for the clock routing guidelines.