Specifications

Intel
®
810E2 Chipset Platform
R
136 Design Guide
5.3. Clock Routing Guidelines
The following table shows the group skew and jitter limits.
Table 37. Group Skew and Jitter Limits at the Pins of the Clock Chip
Signal Group Pin-Pin Skew Cycle-Cycle Jitter Nominal Vdd Skew, Jitter
Measure Point
Processor 175 pS 250 pS 2.5V 1.25V
SDRAM 250 pS 250 pS 3.3V 1.50V
APIC 250 pS 500 pS 2.5V 1.25V
48 MHz 250 pS 500 pS 3.3V 1.50V
3V66 175 pS 500 pS 3.3V 1.50V
PCI 500 pS 500 pS 3.3V 1.50V
REF N/A 1000 pS 3.3V 1.50V
The following table shows the signal group and resistor tolerance.
Table 38. Signal Group and Resistor
Signal Group Resistor
Processor
33
Ω ± 5%
SDRAM
22
Ω ± 5%
DCLK
33
Ω ± 5%
3V66
22
Ω ± 5%
PCI
33
Ω ± 5%
TCLK
22
Ω ± 5%
OCLK/RCLK
33
Ω ± 5%
48 MHz
33
Ω ± 5%
APIC
33
Ω ± 5%
REF
10
Ω ± 5%
The following table shows the layout dimensions for the clock routing.
Note: All the clock signals must be routed on the same layer which reference to a ground plane.