Specifications

Intel
®
810E2 Chipset Platform
R
Design Guide
133
5. Clocking
5.1. Clock Generation
There is only one clock generator component required in an 810E2 chipset system. The CK810E clock
chip is pin compatible with the CK810 clock chip, which comes in a single 56-pin SSOP package.
There is one pin function change in the CK810E relative to the CK810, the REFCLK Reset Strap:
Table 35. REFCLK Reset Strap for CK810 vs. CK810E
At reset APIC Clock Strap System Bus Freq Select (SEL1)
After reset 14 MHz Clock 14 MHz Clock
Reset default Internal Pull-up for 33 MHz APIC Clock
Populate External 10 k
Ω Resistor to
Ground for 16 MHz
Internal Pull-down for 66 MHz or 100 MHz Bus
Freq Select (SEL0)
External Drive to 1 to Select 133 MHz System Bus
The CK810E is a mixed voltage component. Some of the output clocks are 3.3V and some of the output
clocks are 2.5V. As a result, the CK810E device requires both 3.3V and 2.5V. These power supplies
should be as clean as possible. Noise in the power delivery system for the clock driver can cause noise on
the clock lines. The CK810E provides the following clock frequencies.
Table 36. Intel
®
810E2 Chipset Clocks
Number Clock Frequency
3 Processor Clocks 66/100/133 MHz
9 SDRAM Clocks 100 MHz
8 PCI Clocks 33 MHz
2 APIC Clocks 16.67/33 MHz
2 48 MHz Clocks 48 MHz
2 3V66 MHz Clocks 66 MHz
1 REF Clock 14.31818 MHz
The DCLKREF signal from the external clock synthesizer to the GMCH is a 48 MHz signal. This signal
has no length requirements, except those specified in the Design Guide. However, care in routing this
signal relative to the DIMM slots is important. Future board designs should attempt to route the
DCLKREF trace so that the trace is not parallel to the DIMM slots or does not pass underneath the
DIMM slots. This prevents noise coupling of memory-related signals into the 48 MHz clock signal.