Specifications

Intel

810E2 Chipset Platform

130 Design Guide

4.3.4. Clock Routing

Analog simulations are required to ensure clock net signal quality and skew is acceptable. The system

clock skew must be kept to a minimum (The calculations and simulations for the example topology given

in this document have a total clock skew of 200 ps and 150 ps of clock jitter). For a given design, the

clock distribution system, including the clock components, must be evaluated to ensure these same values

are valid assumptions. Each processor’s datasheet specifies the clock signal quality requirements. To

help meet these specifications, follow these general guidelines:

• Tie clock driver outputs if clock buffer supports this mode of operation.

• Match the electrical length and type of traces on the PCB (microstrip and stripline may have

different propagation velocities).

• Maintain consistent impedance for the clock traces.

 Minimize the number of vias in each trace.

 Minimize the number of different trace layers used to route the clocks.

 Keep other traces away from clock traces.

• Lump the loads at the end of the trace if multiple components are to be supported by a single clock

output.

• Have equal loads at the end of each network.

The ideal way to route each clock trace is on the same single inner layer, next to a ground plane, isolated

from other traces, with the same total trace length, to the same type of single load, with an equal length

ground trace parallel to it, and driven by a zero skew clock driver. When deviations from ideal are

required, going from a single layer to a pair of layers adjacent to power/ground planes would be a good

compromise. The fewer number of layers the clocks are routed on, the smaller the impedance difference

between each trace is likely to be. Maintaining an equal length and parallel ground trace for the total

length of each clock ensures a low inductance ground return and produces the minimum current path

loop area. (The parallel ground trace will have lower inductance than the ground plane because of the

mutual inductance of the current in the clock trace.)

4.4. Definitions of Flight Time Measurements/ Corrections

and Signal Quality

Acceptable signal quality must be maintained over all operating conditions to ensure reliable operation.

Signal Quality is defined by four parameters: Overshoot, Undershoot, Settling Limit, and Ringback.

Timings are measured at the pins of the driver and receiver, while signal integrity is observed at the

receiver chip pad. When signal integrity at the pad violates the following guidelines and adjustments

need to be made to flight time, the adjusted flight time obtained at the chip pad can be assumed to have

been observed at the package pin, usually with a small timing error penalty.