Specifications

Intel
®
810E2 Chipset Platform
R
Design Guide 13
1. Introduction
This design guide provides motherboard design guidelines for Intel
®
810E2 chipset systems. These
design guidelines have been developed to ensure maximum flexibility for board designers while reducing
the risk of board related issues. In addition to design guidelines, this document discusses 810E2 chipset
system design issues (e.g., thermal requirements).
The debug recommendations should be consulted when debugging an 810E2 chipset system. However,
the debug recommendations should be understood before completing board design to ensure that the
debug port, in addition to other debug features, will be implemented correctly.
1.1. About This Design Guide
This design guide is intended for hardware designers who are experienced with PC architectures and
board design. The design guide assumes that the designer has a working knowledge of the vocabulary
and practices of PC hardware design.
• Chapter 1, “Introduction”—This chapter introduces the designer to the organization and purpose of
this design guide, and provides a list of references of related documents. This chapter also provides
an overview of the 810E2 chipset.
• Chapter 2, “PGA370 Processor Design Guidelines”—This chapter provides design guidelines for
the PGA370 processor including processor-specific layout guidelines.
• Chapter 3, “Layout and Routing Guidelines”—This chapter provides a detailed set of motherboard
layout and routing guidelines, except for processor-specific layout guidelines. The motherboard
functional units are covered (e.g., chipset component placement, system bus routing, system
memory layout, display cache interface, hub interface, IDE, AC’97, USB, interrupts, SMBUS, PCD,
LPC/ FWH Flash BIOS, and RTC). For the PGA370 processor specific layout guidelines, refer to
Chapter 2.
• Chapter 4, “Advanced System Bus Design”—The goal of this chapter is to provide the system
designer with the information needed for the implementation of 133 MHz and 100 MHz single
processor AGTL+ bus PCB layout.
• Chapter 5, “Clocking”— This chapter provides motherboard clocking guidelines (e.g., clock
architecture, routing, capacitor sites, clock power decoupling, and clock skew).
• Chapter 6, “Power delivery” — This chapter includes guidelines regarding power delivery,
decoupling, thermal, and power sequencing.
• Chapter 7, “Design Checklist”— This chapter provides a design review checklist. ATA/66 and
ATA/100 detection, calculation of pull-up/pull-down resistors, minimizing RTC ESD, and power
management signals are also discussed.
• Chapter 8, “Flixible Motherboard Guidelines”— This chapter includes guidelines regarding power
deliver, decoupling, thermal, and power sequencing.
• Chapter 9, “Third Party Vendor Information”— This chapter includes information regarding various
third-party vendors who provide products to support the 810E2 chipset.
• Appendix A, “Intel
®
810E2 Chipset Platform Reference Schematics”— This appendix includes
schematics for the 810E2 Reference Board