Specifications

Intel
®
810E2 Chipset Platform
R
Design Guide
129
Figure 77. One Layer with Multiple Reference Planes
1lay_Mult_refplane.vsd
Ground
Signal Layer A
Power
4.3.3.2. High Frequency Decoupling
This section contains several high frequency decoupling recommendations that will improve the return
path for an AGTL+ signal. These design recommendations will likely reduce the amount of SSO effects.
Just as layer switching and multiple reference planes can create discontinuities in an AGTL+ signal
return path, discontinuities may also occur when a signal transitions between the baseboard and cartridge.
Therefore, providing adequate high-frequency decoupling across VCC
CORE
and ground at the SC242
connector interface on the baseboard will minimize the discontinuity in the signal’s reference plane at
this junction. Note that these additional high-frequency decoupling capacitors are in addition to the high-
frequency decoupling already on the processor.
Transmission line geometry also influences the return path of the reference plane. The following are
decoupling recommendations that take this into consideration:
• A signal that transitions from a stripline to another stripline should have close proximity decoupling
between all four reference planes.
• A signal that transitions from a stripline to a microstrip (or vice versa) should have close proximity
decoupling between the three reference planes.
• A signal that transitions from a stripline or microstrip through vias or pins to a component (Intel
82810E GMCH, etc.) should have close proximity decoupling across all involved reference planes
to ground for the device.