Specifications

Intel
®
810E2 Chipset Platform
R
128 Design Guide
When it is not possible to route the entire AGTL+ signal on a single VSS referenced layer, there are
methods to reduce the effects of layer switches. The best alternative is to allow the signals to change
layers while staying referenced to the same plane (see Figure 74). Figure 75 shows another method of
minimizing layer switch discontinuities, but may be less effective than Figure 74. In this case, the signal
still references the same type of reference plane (ground). In such a case, it is important to stitch
(i.e., connect) the two ground planes together with vias in the vicinity of the signal transition via.
Figure 74. Layer Switch with One Reference Plane
lay_sw_1refplane.vsd
Signal Layer A
Signal Layer B
Ground Plane
Figure 75. Layer Switch with Multiple Reference Planes (same type)
lay_sw_Mult_refplane.vsd
Signal Layer A
Signal Layer B
Layer
Layer
Ground Plane
Ground Plane
When routing and stackup constraints require that an AGTL+ signal reference VCC or multiple planes,
special care must be given to minimize the SSO impact on timing and noise margin. The best method of
reducing adverse effects is to add high-frequency decoupling wherever the transitions occur, as shown in
Figure 76 and Figure 77. Such decoupling should, again, be in the vicinity of the signal transition via and
use capacitors with minimal effective series resistance (ESR) and effective series inductance (ESL).
When placing the caps, it is recommended to space the VSS and VCC vias as close as possible and/or
use dual vias since the via inductance may sometimes be higher than the actual capacitor inductance.
Figure 76. Layer Switch with Multiple Reference Planes
lay_sw_Mult_refplane2.vsd
Signal Layer A
Ground Plane
Power Plane
Signal Layer B
Layer
Layer