Specifications

Intel
®
810E2 Chipset Platform
R
Design Guide
127
4.3.2. Effective Impedance and Tolerance/Variation
The impedance of the PCB needs to be controlled when the PCB is fabricated. The method of specifying
control of the impedance needs to be determined to best suit each situation. Using stripline transmission
lines (where the trace is between two reference planes) is likely to give better results than microstrip
(where the trace is on an external layer using an adjacent plane for reference with solder mask and air on
the other side of the trace). This is in part due to the difficulty of precise control of the dielectric constant
of the solder mask, and the difficulty in limiting the plated thickness of microstrip conductors, which can
substantially increase crosstalk.
The effective line impedance (Z
EFF
) is recommended to be 60 Ω ±15%, where Z
EFF
is defined by
“Effective Impedance” equation
.
4.3.3. Power/Reference Planes, PCB Stackup, and High Frequency
Decoupling
4.3.3.1. Power Distribution
Designs using the Intel Pentium III processor require several different voltages. The following paragraphs
describe some of the impact of two common methods used to distribute the required voltages. Refer to
the Flexible Motherboard Power Distribution Guidelines for more information on power distribution.
The most conservative method of distributing these voltages is for each of them to have a dedicated
plane. If any of these planes are used as an “AC ground” reference for traces to control trace impedance
on the board, then the plane needs to be AC-coupled to the system ground plane. This method may
require more total layers in the PCB than other methods. A 1 ounce/ft
2
thick copper is recommended for
all power and reference planes.
A second method of power distribution is to use partial planes in the immediate area needing the power,
and to place these planes on a routing layer on an as-needed basis. These planes still need to be
decoupled to ground to ensure stable voltages for the components being supplied. This method has the
disadvantage of reducing area that can be used to route traces. These partial planes may also change the
impedance of adjacent trace layers. (For instance, the impedance calculations may have been done for
microstrip geometry, and adding a partial plane on the other side of the trace layer may turn the
microstrip into a stripline.)
It is strongly recommended that baseboard stackup be arranged such that AGTL+ signals are referenced
to a ground (VSS) plane, and that the AGTL+ signals do not traverse multiple signal layers. Deviating
from either guideline can create discontinuities in the signal’s return path that can lead to large SSO
effects that degrade timing and noise margin. Designing an AGTL+ platform incorporating
discontinuities will expose the platform to a risk that is very hard to predict in pre-layout simulation. The
figure below shows the ideal case where a particular signal is routed entirely within the same signal layer,
with a ground layer as the single reference plane.
Figure 73. One Signal Layer and One Reference Plane
Ground Plane
Signal Layer A
1lay_1ref-plane.vsd