Specifications

Intel
®
810E2 Chipset Platform
R
Design Guide
123
4.1.6.3. Flight Time Hardware Validation
When a measurement is made on the actual system, T
CO
and flight time do not need T
REF
correction since
these are the actual numbers. These measurements include all of the effects pertaining to the driver-
system interface and the same is true for the T
CO
. Therefore the addition of the measured T
CO
and the
measured flight time must be equal to the valid delay calculated above.
Changes in flight time due to crosstalk, noise, and other effects.
4.2. Theory
4.2.1. AGTL+
AGTL+ is the electrical bus technology used for the processor bus. This is an incident wave switching,
open-drain bus with external pull-up resistors that provide both the high logic level and termination at
each load. The processor AGTL+ drivers contain a full-cycle active pull-up device to improve system
timings. The AGTL+ specification defines:
Termination voltage (V
TT
).
Receiver reference voltage (V
REF
) as a function of termination voltage (V
TT
).
processor termination resistance (R
TT
).
Input low voltage (V
IL
).
Input high voltage (V
IH
).
NMOS on resistance (R
ONN
).
PMOS on resistance (R
ONP
).
Edge rate specifications.
Ringback specifications.
Overshoot/Undershoot specifications.
Settling Limit.
4.2.2. Timing Requirements
The system timing for AGTL+ is dependent on many things. Each of the following elements combine to
determine the maximum and minimum frequency the AGTL+ bus can support:
The range of timings for each of the agents in the system.
Clock to output (T
CO
). (Note that the system load is likely to be different from the
“specification” load therefore the T
CO
observed in the system might not be the same as the T
CO
from the specification.)
The minimum required setup time to clock (T
SU_MIN
) for each receiving agent.
The range of flight time between each component. This includes:
The velocity of propagation for the loaded printed circuit board [S
EFF
].
The board loading impact on the effective T
CO
in the system.
The amount of skew and jitter in the system clock generation and distribution.
Changes in flight time due to crosstalk, noise, and other effects.