Specifications

Intel
®
810E2 Chipset Platform
R
122 Design Guide
4.1.6.2. Flight Time Simulation
As defined in Chapter 1, flight time is the time difference between a signal crossing V
REF
at the input pin
of the receiver, and the output pin of the driver crossing V
REF
were it driving a test load. The timings in
the tables and topologies discussed in this guideline assume the actual system load is 50 Ω and is equal to
the test load. While the DC loading of the AGTL+ bus in a DP mode is closer to 25 Ω, AC loading is
approximately 29 Ω since the driver effectively “sees” a 56 Ω termination resistor in parallel with a 60 Ω
transmission line on the cartridge.
Figure 70. Test Load vs. Actual System Load
V
TT
Q
Q
SET
CLR
D
Vcc
CLK
R
TEST
Test Load
Driver
Pin
Driver
Pad
T
REF
T
CO
I/O Buffer
Q
Q
SET
CLR
D
Vcc
CLK
Driver
Pad
T
FLIGHTSYSTE
I/O Buffer
V
TT
R
TT
Actual
System
Load
Receiver
Pin
test_actual_load.vsd
The figure above shows the different configurations for T
CO
testing and flight time simulation. The flip-
flop represents the logic input and driver stage of a typical AGTL+ I/O buffer. T
CO
timings are specified
at the driver pin output. T
FLIGHT-SYSTEM
is usually reported by a simulation tool as the time from the driver
pad starting its transition to the time when the receiver’s input pin sees a valid data input. Since both
timing numbers (T
CO
and T
FLIGHT-SYSTEM
) include propagation time from the pad to the pin, it is necessary
to subtract this time (T
REF
) from the reported flight time to avoid double counting. T
REF
is defined as the
time that it takes for the driver output pin to reach the measurement voltage, V
REF
, starting from the
beginning of the driver transition at the pad. T
REF
must be generated using the same test load for T
CO
.
Intel provides this timing value in the AGTL+ I/O buffer models.
In this manner, the following valid delay equation is satisfied:
Valid Delay Equation
Valid Delay = T
CO
+ T
FLIGHT-SYS
- T
REF
= T
CO-MEASURED
+ T
FLIGHT-MEASURED
This valid delay equation is the total time from when the driver sees a valid clock pulse to the time when
the receiver sees a valid data input.