Specifications

Intel
®
810E2 Chipset Platform
R
120 Design Guide
Table 34 contains the trace width:space ratios assumed for this topology. The crosstalk cases considered
in this guideline involve three types: Intragroup AGTL+, Intergroup AGTL+, and AGTL+ to non-
AGTL+.
Intra-group AGTL+ crosstalk involves interference between AGTL+ signals within the same group (See
Section 4.3). Intergroup AGTL+ crosstalk involves interference from AGTL+ signals in a particular
group to AGTL+ signals in a different group. An example of AGTL+ to non-AGTL+ crosstalk is when
CMOS and AGTL+ signals interfere with each other.
Table 34. Trace Width Space Guidelines
Crosstalk Type Trace Width:Space Ratio
Intragroup AGTL+ (same group AGTL+)
5:10 or 6:12
Intergroup AGTL+ (different group AGTL+)
5:15 or 6:18
AGTL+ to non-AGTL+
5:20 or 6:24
The spacing between the various bus agents causes variations in trunk impedance and stub locations.
These variations cause reflections that can cause constructive or destructive interference at the receivers.
A reduction of noise may be obtained by a minimum spacing between the agents. Unfortunately, tighter
spacing results in reduced component placement options and lower hold margins. Therefore, adjusting
the inter-agent spacing may be one way to change the network’s noise margin, but mechanical constraints
often limit the usefulness of this technique. Always be sure to validate signal quality after making any
changes in agent locations or changes to inter-agent spacing.
There are six AGTL+ signals that can be driven by more than one agent simultaneously. These signals
may require more attention during the layout and validation portions of the design. When a signal is
asserted (driven low) by two or more agents on the same clock edge, the two falling edge wave fronts
will meet at some point on the bus and can sum to form a negative voltage. The ring- back from this
negative voltage can easily cross into the overdrive region. The signals are AERR#, BERR#, BINIT#,
BNR#, HIT#, and HITM#.
This section addresses AGTL+ layout for both 1 and 2-way 133 MHz/100 MHz processor/Intel 810E2
chipset systems. Power distribution and chassis requirements for cooling, connector location, memory
location, etc., may constrain the system topology and component placement location; therefore,
constraining the board routing. These issues are not directly addressed in this document. Chapter 1
contains a listing of several documents that address some of these issues.
4.1.5. Post-Layout Simulation
Following layout, extract the interconnect information for the board from the CAD layout tools. Run
simulations to verify that the layout meets timing and noise requirements. A small amount of “tuning”
may be required; experience at Intel has shown that sensitivity analysis dramatically reduces the amount
of tuning required. The post layout simulations should take into account the expected variation for all
interconnect parameters.
Intel specifies signal integrity at the device pads and therefore recommends running simulations at the
device pads for signal quality. However, Intel specifies core timings at the device pins, so simulation
results at the device pins should be used later to correlate simulation performance against actual system
measurements.