Specifications

Intel
®
810E2 Chipset Platform
R
12 Design Guide
Revision History
Rev. Description Date
-001 • Initial Release January 2001
-002 • Replaced Figure 84. Power Delivery Map
• Revised Section 7.2.6, ICH2 Checklist, Interrupt interface, APIC
• Revised Section 7.2.16, Power, ICH2 Checklist: Recommendations for
5V_REF_SUS
• Revised Section 6.4.3, 3.3V/5VREF Sequencing
• Added Section 3.20.8, Power-well Isolation Control
• Revised Figure 49. Trace Routing in General Trace Routing Considerations,
Section 3.21.2.1
• Added SUSCLK to ICH2 Checklist Section 7.2.13, RTC
• Added Section 6.5, Power_Supply PS_ON Considerations
• Revised ICH2 Checklist Section 7.2.9, Power Management
• Revised Section 3.15, USB
• Added RTCRST# to ICH2 Checklist Section 7.2.13, RTC
• Added 82562ET/EM Disable Guidelines, Section 3.21.4.6
• Revised Section 3.22.2., FWH Vpp Design Guidelines
• Revised Section 3.21.5, 82562ET / 82562EH Dual Footprint Guidelines
• Revised Section 3.1, General Recommendations
• Revised ICH2 Checklist Section 7.2.13, RTC, RTCX1-RTCX2
• Revised RTC Crystal, Section 3.20.1
• Revised ICH2 Checklist, Section 7.2.9, Power Management, PWRBTN#
• Revised ICH2 Checklist, PCI Interface, Section 7.2.1, PME#
• Revised VCCcore Decoupling Design, Section 2.2.10.1
• Revised Figure 23 and Figure 24 in Compensation, Section 3.6.4
• Revised 82562ET / 82562EH Dual Footprint Guidelines, Section 3.21.5
• Revised 82562ET / 82562EM Termination Resistors, Section 3.21.4.3
• Revised General Trace Routing Considerations, Section 3.21.2.1
• Revised Table 23, in Point-To-Point Interconnect, Section 3.21.1.2
• Revised LAN Layout Guidelines, Section 3.21
August 2002