Specifications

Intel
®
810E2 Chipset Platform
R
Design Guide
119
The transmission line package models must be inserted between the output of the buffer and the net it is
driving. Likewise, the package model must also be placed between a net and the input of a receiver
model. Editing the simulator’s net description or topology file generally does this.
Intel has found wide variation in noise margins when varying the stub impedance and the PCB’s Z0 and
S0. Intel, therefore, recommends that PCB parameters be controlled as tightly as possible, with a
sampling of the allowable Z0 and S0 simulated. The Pentium
III processor nominal effective line
impedance is 65 Ω ±15%. Future Pentium
III processor effective line impedance (ZEFF ) may be 60
Ω ±15%. Intel recommends the baseboard nominal effective line impedance to be at 60 Ω ±15% for the
recommended layout guidelines to be effective. Intel also recommends running uncoupled simulations
using the Z
0 of the package stubs and performing fully coupled simulations if increased accuracy is
needed or desired. Accounting for crosstalk within the device package by varying the stub impedance
was investigated and was not found to be sufficiently accurate. This lead to the development of full
package models for the component packages.
4.1.4. Place and Route Board
4.1.4.1. Estimate Component to Component Spacing for AGTL+ Signals
Estimate the number of layers that will be required. Then determine the expected interconnect distances
between each of the components on the AGTL+ bus. Using the estimated interconnect distances, verify
that the placement can support the system timing requirements.
The required bus frequency and the maximum flight time propagation delay on the PCB determine the
maximum network length between the bus agents. The minimum network length is independent of the
required bus frequency. Table 32 and Table 33 assume values for CLK
SKEW and CLKJITTER (parameters
that are controlled by the system designer). To reduce system clock skew to a minimum, clock buffers
that allow their outputs to be tied together are recommended. Intel strongly recommends running analog
simulations to ensure that each design has adequate noise and timing margin.
4.1.4.2. Layout and Route Board
Route the board satisfying the estimated space and timing requirements. Also stay within the solution
space set from the pre-layout sweeps. Estimate the printed circuit board parameters from the placement
and other information including the following general guidelines:
• Distribute V
TT
with a power plane or a partial power plane. If this cannot be accomplished, use as
wide a trace as possible and route the V
TT
trace with the same topology as the AGTL+ traces.
• Keep the overall length of the bus as short as possible (but do not forget minimum component- to-
component distances to meet hold times).
• Plan to minimize crosstalk with the following guidelines developed for the example topology given
(signal spacing recommendations were based on fully coupled simulations; spacing may be
decreased based upon the amount of coupled length).
 Use an intragroup AGTL+ spacing to line width to dielectric thickness ratio of at least 2:1:1 for
microstrip geometry. If e
r
= 4.5, this should limit coupling to 3.4%. For example, intragroup
AGTL+ routing could use 10 mil spacing, 5 mil traces, and a 5 mil prepreg between the signal
layer and the plane it references (assuming a 4-layer motherboard design).
 Minimize the dielectric process variation used in the PCB fabrication.
 Eliminate parallel traces between layers not separated by a power or ground plane.