Specifications

Intel
®
810E2 Chipset Platform
R
116 Design Guide
Table 32 and Table 33 are derived assuming:
• CLK
SKEW = 0.2 ns (Note: Assumes clock driver pin-to-pin skew is reduced to 50 ps by tying two
host clock outputs together (“ganging”) at clock driver output pins, and the PCB clock routing skew
is 150 ps. System timing budget must assume 0.175 ns of clock driver skew if outputs are not tied
together and a clock driver that meets the CK98 clock driver specification is being used.)
• CLK
JITTER = 0.250 ns
Some clock driver components may not support ganging the outputs together. Be sure to verify with your
clock component vendor before ganging the outputs. See the appropriate Intel 810E chipset
documentation and CK98 Clock Synthesizer/Driver Specification for details on clock skew and jitter
specifications. Refer to the “Clocking” chapter for host clock routing details.
Table 32. Example T Calculations for 133 MHz Bus
1
Driver Receiver Clk
Period
2
T
CO_MAX TSU_MIN ClkSKEW ClkJITTER MADJ Recommended
T
FLT_MAX
3
Processor Processor 7.50 2.7 1.20 0.20 0.250 0.40 2.75
Processor 82810E
GMCH
7.50 2.7 2.27 0.20 0.250 0.40 1.68
Intel
®
82810E
GMCH
Processor 7.50 3.63 1.20 0.20 0.25 0.40 1.82
NOTES:
1. All times in nanoseconds.
2. BCLK period = 7.50 ns @ 133.33 MHz.
3. The flight times in this column include margin to account for the following phenomena that Intel has observed
when multiple bits are switching simultaneously. These multi-bit effects can adversely affect flight time and
signal quality and are sometimes not accounted for in simulation. Accordingly, maximum flight times depend on
the baseboard design and additional adjustment factors or margins are recommended.
- SSO push-out or pull-in.
- Rising or falling edge rate degradation at the receiver caused by inductance in the current return path,
requiring extrapolation that causes additional delay.
- Crosstalk on the PCB and internal to the package can cause variation in the signals.
There are additional effects that
may not necessarily be covered by the multi-bit adjustment factor and should
be budgeted as appropriate to the baseboard design. Examples include:
- The effective board propagation constant (S
EFF ), which is a function of:
• Dielectric constant
(r ) of the PCB material.
• The type of trace connecting the components (stripline or microstrip).
• The length of the trace and the load of the components on the trace. Note that the board propagation
constant multiplied by the trace length is a
component of the flight time but not necessarily equal to the
flight time.
Table 33. Example TFLT_MIN Calculations (Frequency Independent)
Driver Receiver THOLD ClkSKEW TCO_MIN Recommended
T
FLT_MIN
Processor Processor 0.8 0.2 -0.1 1.2
Processor 82810E GMCH 0.28 0.2 -0.1 0.58
Intel
®
82810E
GMCH
Processor 0.8 0.2 0.5 0.5
NOTE: All times in nanoseconds.