Specifications

Intel
®
810E2 Chipset Platform
R
Design Guide
115
There are multiple cases to consider. Note that while the same trace connects two components,
component A and component B, the minimum and maximum flight time requirements for component A
driving component B as well as component B driving component A must be met. The cases to be
considered are:
• Processor driving processor
• Processor driving chipset
• Chipset driving processor
A designer using components other than those listed above must evaluate additional combinations of
driver and receiver.
Table 31. AGTL+ Parameters for Example Calculations
1,2
IC Parameters Intel
®
Pentium
®
III
processor core at
133 MHz Bus (ns)
Intel
®
82810E
GMCH (ns)
Notes
Clock to Output maximum (TCO_MAX ) 2.7 3.6 4
Clock to Output minimum (TCO_MIN ) -0.1 0.5 4
Setup time (TSU_MIN ) 1.2 2.27 3,4
Hold time (THOLD ) 0.8 0.28 4
NOTES:
1. All times in nanoseconds.
2.
Numbers in table are for reference only. These timing parameters are subject to change. Please check the
appropriate component documentation for valid timing parameter values.
3. T
SU_MIN
= 1.9 ns assumes the 82810E GMCH sees a minimum edge rate equal to 0.3 V/ns.
4. The Pentium III substrate nominal impedance is set to 65
Ω ±15%. Future Pentium III processor substrate may
be set at 60
Ω ±15%
Table 31 lists the AGTL+ component timings of the processors and 82810E GMCH defined at the pins.
These timings are for reference only.
Table 32 gives an example AGTL+ initial maximum flight time and Table 33 is an example minimum
flight time calculation for a 133 MHz, 2-way Pentium
III processor/Intel 810E2 chipset system bus. Note
that assumed values for clock skew and clock jitter were used. Clock skew and clock jitter values are
dependent on the clock components and distribution method chosen for a particular design and must be
budgeted into the initial timing equations as appropriate for each design.
Intel highly recommends adding margin as shown in the “M
ADJ ” column to offset the degradation
caused by SSO push-out and other multi-bit switching effects. The “Recommended T
FLT_MAX ” column
contains the recommended maximum flight time after incorporating the M
ADJ value. If edge rate,
ringback, and monotonicity requirements are not met, flight time correction must first be performed as
documented in the Intel
®
Pentium
®
II Processor Developer’s Manual with the additional requirements
noted in Section 4.1. The commonly used “textbook” equations used to calculate the expected signal
propagation rate of a board are included in that section.
Simulation and control of baseboard design parameters can ensure that signal quality and maximum and
minimum flight times are met. Baseboard propagation speed is highly dependent on transmission line
geometry configuration (stripline vs. microstrip), dielectric constant, and loading. This layout guideline
includes high-speed baseboard design practices that may improve the amount of timing and signal quality
margin. The magnitude of M
ADJ is highly dependent on baseboard design implementation (stackup,
decoupling, layout, routing, reference planes, etc.) and needs to be characterized and budgeted
appropriately for each design.