Specifications

Intel
®
810E2 Chipset Platform
R
100 Design Guide
3.23. FWH Decoupling
A 0.1 µF capacitor should be placed between the Vcc supply pins and the Vss ground pins to decouple
high frequency noise, which may affect the programmability of the device. Additionally, a 4.7 µF
capacitor should be placed between the Vcc supply pins and the Vss ground pin to decouple low
frequency noise. The capacitors should be placed no further than 390 mils from the Vcc supply pins.
3.24. Processor PLL Filter Recommendation
3.24.1. Processor PLL Filter Recommendation
All Celeron processors have internal PLL clock generators that are analog and require quiet power
supplies to minimize jitter.
3.24.2. Topology
The general desired topology is shown in the following figure. Not shown are parasitic routing and local
decoupling capacitors. Excluded from the external circuitry are parasitics associated with each
component.
Figure 60. Filter Topology
v004
RL
C
PLL2
PLL1
PLL
VSS = 0V
370-Pin
Socket
V
CC
CORE
3.24.3. Filter Specification
The function of the filter is to protect the PLL from external noise through low-pass attenuation. In
general, the low-pass description forms an adequate description for the filter.
The low-pass specification, with input at VCC
CORE
and output measured across the capacitor, is as
follows:
< 0.2 dB gain in pass band
< 0.5 dB attenuation in pass band (see DC drop in next set of requirements)
> 34 dB attenuation from 1 MHz to 66 MHz
> 28 dB attenuation from 66 MHz to core frequency