Specifications

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Intel

810E2 Chipset Platform

10 Design Guide

Tables

Table 1. Platform Pin Definition Comparison for Single Processor Designs ............................26

Table 2. Intel

Pentium

III Processor and Intel

82810E GMCH AGTL+ Parameters for

Example Calculations........................................................................................................27

Table 3. Example T

FLT_MIN

Calculations for 133 MHz Bus

.......................................................28

Table 4. Example TFLT_MIN Calculations (Frequency Independent)

.......................................28

Table 5. Segment Descriptions and Lengths for Figure 2

......................................................29

Table 6. Trace Width:Space Guidelines...................................................................................29

Table 7. Routing Guidelines for Non-AGTL+ Signals ...............................................................31

Table 8. Intel

CK810E Reset Strapping Matrix .......................................................................33

Table 9. Examples for CLKREF Divider Circuit........................................................................34

Table 10. Power Up Options ....................................................................................................36

Table 11. Host Frequency Strappings ......................................................................................36

Table 12. System Memory Routing ..........................................................................................46

Table 13. Display Cache Routing (Topology 1) ........................................................................49

Table 14. Display Cache Routing (Topology 2) ........................................................................49

Table 15. Display Cache Routing (Topology 3) ........................................................................50

Table 16. Display Cache Routing (Topology 4) ........................................................................50

Table 17. Decoupling Capacitor Recommendation..................................................................54

Table 18. AC'97 SDIN Pull-down Resistors..............................................................................64

Table 19. Signal Descriptions...................................................................................................67

Table 20. Codec Configurations ...............................................................................................68

Table 21. Pull-up Requirements for SMBus and SMLink .........................................................72

Table 22. LAN Design Guide Section Reference .....................................................................80

Table 23. Single-Solution Interconnect Length Requirements .................................................81

Table 24. LOM/CNR Length Requirements..............................................................................82

Table 25. Inductor...................................................................................................................102

Table 26. Capacitor ................................................................................................................102

Table 27. Resistor ..................................................................................................................102

Table 28. DPLL LC Filter Component Example .....................................................................110

Table 29. Additional DPLL LC Filter Component Example.....................................................111

Table 30. Resistance Values for Frequency Response Curves.............................................112

Table 31. AGTL+ Parameters for Example Calculations

1,2

....................................................115

Table 32. Example T Calculations for 133 MHz Bus

.............................................................116

Table 33. Example TFLT_MIN Calculations (Frequency Independent) ....................................116

Table 34. Trace Width Space Guidelines...............................................................................120

Table 35. REFCLK Reset Strap for CK810 vs. CK810E ........................................................133

Table 36. Intel

810E2 Chipset Clocks...................................................................................133

Table 37. Group Skew and Jitter Limits at the Pins of the Clock Chip ...................................136

Table 38. Signal Group and Resistor .....................................................................................136

Table 39. Layout Dimensions .................................................................................................137

Table 40. Clock Skew Requirements .....................................................................................142

Table 41. Power Sequencing Timing Definitions....................................................................148

Table 42. AGTL+ Connectivity Checklist for 370-Pin Socket Processors ..............................158

Table 43. CMOS Connectivity Checklist for 370-Pin Socket Processors...............................159

Table 44. TAP Checklist for a 370-Pin Socket Processor ......................................................159

Table 45. Miscellaneous Checklist for 370-Pin Socket Processors .......................................160

Table 46. GMCH Checklist .....................................................................................................161

Table 47. System Memory Checklist ......................................................................................162

Table 48. Display Cache Checklist.........................................................................................162

Table 49. Flexible Processor Voltage and Current Guidelines for 1.5V Processors ..............179

Table 50. Flexible Processor Voltage and Current Guidelines for 2.0 V Processors .............180