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Intel

810E2 Chipset Platform

Design Guide

August 2002

Document Number: 298248-002

Summary of content (223 pages)

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R Intel® 810E2 Chipset Platform Design Guide August 2002 Document Number: 298248-002
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® Intel 810E2 Chipset Platform R INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT.
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® Intel 810E2 Chipset Platform R Contents 1. Introduction ................................................................................................................................ 13 1.1. 1.2. 1.3. 2. PGA370 Processor Design Guidelines ...................................................................................... 25 2.1. 2.2. 3. Electrical Differences for Flexible PGA370 Designs ..................................................... 25 PGA370 Socket Definition Details .................
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® Intel 810E2 Chipset Platform R 3.5. 3.6. 3.7. 3.8. 3.9. 3.10. 3.11. 3.12. 3.13. 3.14. 3.15. 3.16. 3.17. 3.18. 3.19. 3.20. 3.21. 4 System Memory Routing Example ..............................................................47 3.1.1 3.4.2. System Memory Connectivity ......................................................................48 Display Cache Interface.................................................................................................49 3.5.1. Display Cache Solution Space......
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® Intel 810E2 Chipset Platform R 3.22. 3.23. 3.24. 3.25. 3.26. 4. Advanced System Bus Design................................................................................................. 113 4.1. Design Guide 3.21.2.2. Power and Ground Connections .................................................... 85 3.21.2.3. A 4-Layer Board Design ................................................................. 86 3.21.2.4. Common Physical Layout Issues ...................................................
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® Intel 810E2 Chipset Platform R 4.2. 4.3. 4.4. 5. Clocking....................................................................................................................................133 5.1. 5.2. 5.3. 5.4. 5.5. 5.6. 6. 6.2. 6.3. 6.4. 6.5. Thermal Design Power ................................................................................................144 6.1.1. Power Sequencing.....................................................................................
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® Intel 810E2 Chipset Platform R Interrupt Interface ...................................................................................... 165 7.2.6. 7.2.7. GPIO Checklist.......................................................................................... 166 7.2.8. USB ...................................................................................................... 167 7.2.9. Power Management .................................................................................. 168 7.2.10.
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® Intel 810E2 Chipset Platform R Figures ® Figure 1. Intel 810E2 Chipset System ....................................................................................20 Figure 2. Topology for 370-Pin Socket Designs with Single-Ended Termination (SET) ..........29 Figure 3. Routing for THRMDP and THRMDN.........................................................................31 Figure 4. BSEL[1:0] Circuit Implementation for PGA370 Designs ...........................................33 Figure 5.
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® Intel 810E2 Chipset Platform R ® Figure 51. Intel 82562EH Termination ................................................................................... 90 Figure 52. Critical Dimensions for Component Placement ...................................................... 91 ® Figure 53. Intel 82562ET/82562EM Termination ................................................................... 93 Figure 54. Critical Dimensions for Component Placement ......................................................
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® Intel 810E2 Chipset Platform R Tables Table 1. Platform Pin Definition Comparison for Single Processor Designs ............................26 ® ® ® Table 2. Intel Pentium III Processor and Intel 82810E GMCH AGTL+ Parameters for Example Calculations........................................................................................................27 1 Table 3. Example TFLT_MIN Calculations for 133 MHz Bus .......................................................28 1 Table 4.
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® Intel 810E2 Chipset Platform R Table 51. Flexible Motherboard Processor System Bus AC Guidelines (Clock) at the Processor Pins ........................................................................................................................ 181 Table 52. Processor System Bus AC Guidelines (AGTL+ Signal Group) at the Processor Pins......................................................................................................................... 182 ® ® Table 53.
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® Intel 810E2 Chipset Platform R Revision History Rev. Description Date -001 • Initial Release January 2001 -002 • Replaced Figure 84. Power Delivery Map August 2002 • Revised Section 7.2.6, ICH2 Checklist, Interrupt interface, APIC • Revised Section 7.2.16, Power, ICH2 Checklist: Recommendations for 5V_REF_SUS • Revised Section 6.4.3, 3.3V/5VREF Sequencing • Added Section 3.20.8, Power-well Isolation Control • Revised Figure 49. Trace Routing in General Trace Routing Considerations, Section 3.
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® Intel 810E2 Chipset Platform R 1. Introduction This design guide provides motherboard design guidelines for Intel® 810E2 chipset systems. These design guidelines have been developed to ensure maximum flexibility for board designers while reducing the risk of board related issues. In addition to design guidelines, this document discusses 810E2 chipset system design issues (e.g., thermal requirements). The debug recommendations should be consulted when debugging an 810E2 chipset system.
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® Intel 810E2 Chipset Platform R Term 14 Definition Suspend-To-RAM (STR) In the STR state, the system state is stored in main memory and all unnecessary system logic is turned off. Only main memory and logic required to wake the system remain powered. Full-power operation During full-power operation, all components on the motherboard remain powered. Note that full-power operation includes both the full-on operating state (S0) and the processor Stop Grant state (S1).
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® Intel 810E2 Chipset Platform R Term Crosstalk Definition The reception on a victim network of a signal imposed by aggressor network(s) through inductive and capacitive coupling between the networks. • Backward Crosstalk - coupling that creates a signal in a victim network that travels in the opposite direction as the aggressor’s signal. • Forward Crosstalk - coupling that creates a signal in a victim network that travels in the same direction as the aggressor’s signal.
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® Intel 810E2 Chipset Platform R Term 16 Definition Pad A feature of a semiconductor die contained within an internal logic package on the S.E.C cartridge substrate used to connect the die to the package bond wires. A pad is only observable in simulation. Pin A feature of a logic package contained within the S.E.C. cartridge used to connect the package to an internal substrate trace. Ringback Ringback is the voltage that a signal rings back to after achieving its maximum absolute value.
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® Intel 810E2 Chipset Platform R 1.1.1.
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® Intel 810E2 Chipset Platform R 1.2. System Overview The 810E2 chipset enhances the performance of the first generation Integrated Graphics chipset designed for the Intel® Celeron® processor and Intel® Pentium® III processor. The graphics accelerator architecture consists of dedicated multi-media engines executing in parallel to deliver high performance 3D, 2D, and motion compensation video capabilities.
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® Intel 810E2 Chipset Platform R 1.2.1. Graphics and Memory Controller Hub (GMCH) The GMCH provides the interconnect between the SDRAM and the rest of the system logic: • • • • • • • • 1.2.2. 421 Mini BGA Integrated Graphics controller 230 MHz RAMDAC Support for the Celeron processor and Pentium III processor with a 66 MHz , 100 MHz, or 133 MHz system bus.
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® Intel 810E2 Chipset Platform R 1.2.3. System Configurations ® Figure 1.
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® Intel 810E2 Chipset Platform R 1.3. Platform Initiatives 1.3.1. Hub Interface As I/O speeds increase, the demand placed on the PCI bus by the I/O bridge has become significant. With the addition of AC’97 and Ultra ATA/100, coupled with the existing USB, I/O requirements could impact PCI bus performance. The 810E2 chipset’s hub interface architecture ensures that the I/O subsystem (both PCI and the integrated I/O features such as IDE, AC’97, USB, etc.), receives adequate bandwidth.
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® Intel 810E2 Chipset Platform R 1.3.7. Firmware Hub (FWH) Flash BIOS The 810E2 chipset platform supports firmware hub BIOS memory sizes up to 8 MB for increased system flexibility. 1.3.8. AC’97 6-Channel Support The Audio Codec ’97 (AC’97) Specification defines a digital interface that can be used to attach an audio codec (AC), a modem codec (MC), an audio/modem codec (AMC), or both an AC and a MC.
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® Intel 810E2 Chipset Platform R a) AC'97 with Audio Codecs (4-Channel Secondary) ICH2 360 EBGA AC’97 Digital Link AC’97 Audio Codec Audio Port AC’97 Audio Codec Audio Port b) AC'97 with Modem and Audio Codecs Modem Port ICH2 360 EBGA AC’97 Digital Link AC’97 Modem CODEC AC’97 Audio/ CODEC Audio Port c) AC'97 with Audio/Modem Codec Modem Port ICH2 360 EBGA AC’97 Digital Link AC’97 Audio/ Modem Codec Audio Port AC97_connections Design Guide 23
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® Intel 810E2 Chipset Platform R 1.3.9. Low Pin Count (LPC) Interface In the 810E2 chipset platform, the Super I/O (SIO) component has migrated to the Low-Pin-Count (LPC) interface. Migration to the LPC interface allows for lower-cost Super I/O designs. The LPC Super I/O component requires the same feature set as traditional Super I/O components. It should include a keyboard and mouse controller, floppy disk controller, and serial and parallel ports.
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® Intel 810E2 Chipset Platform R 2. PGA370 Processor Design Guidelines This chapter provides PGA370 processor design guidelines including the PGA370 socket, Layout Guidelines, BSEL implementation, CLKREF, Undershoot/Overshoot requirements, Reset, Decoupling guidelines, Thermal/EMI differences, and Debug Port changes. The layout guidelines are processorspecific and should be used in conjunction with Chapter 3.
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® Intel 810E2 Chipset Platform R Table 1.
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® Intel 810E2 Chipset Platform R 2.2.1. Layout Guidelines for Intel® Pentium® III Processors The following layout guide supports designs using Celeron processors and the Pentium III processor with the 810E2 chipset. The solution covers system bus speeds of 66/100 MHz for the Celeron processor and 100/133 MHz for the Pentium III processors. The solution proposed in this segment requires the motherboard design to terminate the system bus AGTL+ signals with a 56 Ω ± 5% Rtt.
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® Intel 810E2 Chipset Platform R Table 3. Example TFLT_MIN Calculations for 133 MHz Bus Driver Receiver 1 Clk Period2 TCO_MAX TSU_MIN ClkSKEW ClkJITTER MADJ Recommended TFLT_MIN3 Processor GMCH 7.50 2.70 2.72 0.20 0.25 0.40 3.73 GMCH Processor 7.50 5.35 1.20 0.20 0.25 0.40 2.60 NOTES: 1. All times in nanoseconds. 2. BCLK period = 7.50 ns @ 133.33 MHz. 3.
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® Intel 810E2 Chipset Platform R Figure 2. Topology for 370-Pin Socket Designs with Single-Ended Termination (SET) Vtt 56 Ω 82810E GMCH L(1): L3 L1 L2 PGA370 Socket Z0=60 Ω ±15%. 370pin_set.vsd Table 5. Segment Descriptions and Lengths for Figure 2 1 Segment Description Min length (inches) Max length (inches) L1 + L2 Intel® 82810E GMCH to Rtt Stub 1.90 4.50 L2 PGA370 Pin to Rtt stub 0.0 0.20 L3 Rtt Stub length 0.50 2.50 NOTES: 1.
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® Intel 810E2 Chipset Platform R 2.2.2.1. Motherboard Layout Rules for AGTL+ Signals Minimizing Crosstalk The following general rules will minimize the impact of crosstalk in the high-speed AGTL+ bus design: • Maximize the space between traces. Maintain a minimum of 10 mils (assuming a 5 mil trace) between trace edges wherever possible. It may be necessary to use tighter spacing when routing between component pins.
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® Intel 810E2 Chipset Platform R Table 7. Routing Guidelines for Non-AGTL+ Signals 2.2.2.3.
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® Intel 810E2 Chipset Platform R 2.2.2.4. Additional Considerations • Distribute VTT with a wide trace. A 0.050” minimum trace is recommended to minimize DC losses. Route the VTT trace to all components on the host bus. Be sure to include decoupling capacitors. • The VTT voltage should be 1.5V ± 3% for static conditions and 1.5 V ± 9% for worst case transient condition. • Place resistor divider pairs for VREF generation at the 82810E GMCH component. VREF is also delivered to the processor. 2.2.3.
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® Intel 810E2 Chipset Platform R Figure 4. BSEL[1:0] Circuit Implementation for PGA370 Designs 3.3V 3.3V 1 ΚΩ 3.3V Processor 1 ΚΩ BSEL0 8.2 K Ω BSEL1 14 MHz REFCLK 10 K Ω Note 1 REF CK810E SEL1 SEL0 10 K Ω 10 K Ω LMD29 LMD13 82810E GMCH Notes: 1. If CK810E is installed (66/100 MHz only), this resistor should not be stuffed. SBus_FreqSel_pga370.vsd ® Table 8.
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® Intel 810E2 Chipset Platform R 2.2.5. CLKREF Circuit Implementation The CLKREF input requires a 1.25V source. It can be generated from a voltage divider on the Vcc2.5 or Vcc3.3 sources utilizing 1% tolerance resistors. A 4.7 µF decoupling capacitor should be included on this input. See the following figure and table for example CLKREF circuits. Do not use VTT as the source for this reference! Figure 5. Examples for CLKREF Divider Circuit PGA370 Vcc2.5 PGA370 Vcc3.
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® Intel 810E2 Chipset Platform R 2.2.7. Connecting RESET# and RESET2# on a Flexible PGA370 Design The 810E2 chipset platform designs that support both the Celeron processor and Pentium III processor must route the AGTL+ reset signal from the chipset to two pins on the processor, as well as to the ITP connector. This reset signal is connected to pins AH4 (RESET#) and X4 (RESET#) at the PGA370 socket (See the following figure). Figure 6.
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® Intel 810E2 Chipset Platform R 2.2.8.1. Power-Up/Reset Strap Options Table 10 lists power-up options that are loaded into the 82810E GMCH during cold reset. Table 10. Power Up Options Signal Description LMD[31] XOR Chain Test Select: LMD[31] is set to 0 for normal operation. It must be set to 1 to enter XOR tree mode during reset. This signal must remain 1 during the entire XOR tree test. LMD[30] ALL Z select: If LMD[30] is set to 1, it tri-states all signals during reset.
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® Intel 810E2 Chipset Platform R 2.2.10.1. VCCcore Decoupling Design • Ten or more 4.7 µF capacitors in 1206 packages. All capacitors should be placed within the PGA370 socket cavity and mounted on the primary side of the motherboard. The capacitors are arranged to minimize the overall inductance between VCCCORE/Vss power pins, as shown in the following figure. • 8 ea (min) 1 µF 0612 package placed in the Intel® PGA370 socket cavity. Figure 7. Capacitor Placement on the Motherboard 2.2.10.2.
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® Intel 810E2 Chipset Platform R 2.2.11. Thermal/EMI Differences Heatsink requirements will be different for FC-PGA processors from previous processors using PPGA packaging. The current flexible motherboard guidelines for Pentium III (FC-PGA w/256-K L2 cache) processors calls for 28.4 W. • Increased power density for Pentium III processor (approximately 27 W/cm2). • Different thermal design verification for FC-PGA compared to PPGA packaged processors.
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® Intel 810E2 Chipset Platform R 2.2.13. PGA370 Socket Connector Strapping Option Clarifications of the keep-out zone changes are as follows: • An increase in the height of the heatsink volumetric area from 2.10” to 2.52” including a 0.420” area above the heatsink to allow adequate area for fan inlet air. • Growth in the x direction of the top of the heatsink keep-out zone from 2.55” to 3.
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® Intel 810E2 Chipset Platform R This page is intentionally left blank.
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® Intel 810E2 Chipset Platform R 3. Layout and Routing Guidelines This chapter describes motherboard layout and routing guidelines for 810E2 chipset systems, except for the processor layout guidelines. For the PGA370 processor specific layout guidelines, refer to Chapter 2. This chapter does not discuss the functional aspects of any bus or the layout guidelines for an add-in device. Note: 3.1.
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® Intel 810E2 Chipset Platform R Figure 10. Nominal Board Stackup Component Side Layer 1 (1/2 oz. cu) 4.5 mil Prepreg Power Plane Layer 2 (1 oz. cu) ~48 mil Core 62 mils Total Thickness Ground Layer 3 (1 oz. cu) 4.5 mil Prepreg Solder SIde Layer 4 (1/2 oz. cu) stackup.vsd 3.1 Component Quadrant Layouts Figure 11.
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® Intel 810E2 Chipset Platform R ® Figure 12. Intel ICH2 Quadrant Layout (Top View) Hub interface Processor IDE LAN ICH2 360 EBGA SM bus AC'97 PCI LPC USB quad_ICH2 The diagram in the previous figure illustrates the relative signal quadrant locations on the ICH2 ballout. It does not represent the actual ballout. Refer to the Intel® 82801BA I/O Controller Hub 2 (ICH2) Datasheet for the actual ballout.
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® Intel 810E2 Chipset Platform R Figure 13. Firmware Hub (FWH) Packages 4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 FWH Interface (40-Lead TSOP) 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 3 2 1 32 31 30 5 29 6 28 7 FWH Interface 27 8 (32-Lead PLCC, 0.450" x 0.550") 26 9 25 Top View 10 24 11 23 12 22 13 21 14 15 16 17 18 19 20 pck_fwh.
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® Intel 810E2 Chipset Platform R 3.3. Intel® 810E2 Chipset Component Placement The assumptions for component placement are: • uATX form factor • 4-Layer motherboard • Single-sided assembly Figure 14.
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® Intel 810E2 Chipset Platform R 3.4. System Memory Layout Guidelines 3.4.1. System Memory Solution Space Figure 15. System Memory Topologies GMCH DIMM0 Topology 1 10 ohm A B 10 ohm A Topology 2 DIMM1 C Topology 3 A D Topology 4 A D Topology 5 A E F G G Table 12. System Memory Routing Trace Lengths (inches) Trace (mils) Signal Space Opt.1 5 10 Opt.2 5 Opt.3 Max Min C Min Max Min E Max F 8 3 10 8 5 10 8 Opt.1 4 10 8 3 Opt.2 4 10 8 Opt.
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® Intel 810E2 Chipset Platform R 3.1.1 System Memory Routing Example Figure 16.
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® Intel 810E2 Chipset Platform R 3.4.2. System Memory Connectivity Figure 17.
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® Intel 810E2 Chipset Platform R 3.5. Display Cache Interface Figure 18. Display Cache (Topology 1) 1Mx16 A 3.5.1. Display Cache Solution Space Table 13. Display Cache Routing (Topology 1) Trace (mils) Signal LMD[31:0], LDQM[3:0] A (inches) Topology Width Spacing Min Max 1 5 7 1 5 NOTES: 1. Trace Length (inches) Figure 19. Display Cache (Topology 2) C 1Mx16 C 1Mx16 B Table 14.
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® Intel 810E2 Chipset Platform R Figure 20. Display Cache (Topology 3) 22 Ohms D F 1Mx16 F 1Mx16 E Table 15. Display Cache Routing (Topology 3) Trace (units=mils) Signal TCLK D (inches) E (inches) F (inches) Topology Width Spacing Length Min Max Min Max 3 5 7 0.5 1.5 2.5 0.75 1.25 Figure 21. Display Cache (Topology 4) G OCLK 33 Ohms H RCLK Table 16.
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® Intel 810E2 Chipset Platform R 3.6. Hub Interface The 810E2 chipset’s GMCH ball assignment and ICH2 ball assignment have been optimized to simplify hub interface routing. It is recommended that the hub interface signals be routed directly from the GMCH to the ICH2 on the top signal layer. Refer to the following figure. The hub interface is divided into two signal groups: data signals and strobe signals.
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® Intel 810E2 Chipset Platform R 3.6.2. Strobe Signals Due to their differential nature, the hub interface strobe signals should be 5 mils wide and routed 20 mils apart. This strobe pair should be a minimum of 20 mils from any adjacent signals. The maximum length for the strobe signals is 7”, and the two strobes should be the same length. Additionally, the trace length for each data signal should be matched to the trace length of the strobes, within ±0.1”. 3.6.3.
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® Intel 810E2 Chipset Platform R Figure 23. Single Hub Interface Reference Divider Circuit 1.8V 300 Ω GM CH ICH HUBREF HUBREF 0.01 uF 300 Ω 0.01 uF 0.1 uF HubRef1 Figure 24. Locally Generated Hub Interface Reference Dividers 1.8V GM CH 1.8V 300 Ω 300 Ω HUBREF ICH HUBREF 300 Ω 0.01 uF 0.
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® Intel 810E2 Chipset Platform R 3.7. Intel® ICH2 3.7.1. Decoupling The ICH2 is capable of generating large current swings when switching between logic High and logic Low. This condition could cause the component voltage rails to drop below specified limits. To avoid this type of situation, ensure that the appropriate amount of bulk capacitance is added in parallel to the voltage input pins.
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® Intel 810E2 Chipset Platform R ® Figure 25. Intel ICH2 Decoupling Capacitor Layout 3.3V Core 1.8V Core 1.8V Standby 3.3V Standby 1.8V Standby 5V Ref 3.8. 3.3V Core decouple_cap_layout 1.8V/3.3V Power Sequencing The ICH2 has two pairs of associated 1.8V and 3.3V supplies. These are Vcc1_8, Vcc3_3 and VccSus1_8, VccSus3_3. These pairs are assumed to power up and power down together. The difference between the two associated supplies must never be greater than 2.0V. The 1.
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® Intel 810E2 Chipset Platform R The following figure shows an example power-on sequencing circuit that ensures the “2V Rule” is obeyed. This circuit uses a NPN (Q2) and PNP (Q1) transistor to ensure the 1.8V supply tracks the 3.3V supply. The NPN transistor controls the current through PNP from the 3.3V supply into the 1.8V power plane by varying the voltage at the base of the PNP transistor. By connecting the emitter of the NPN transistor to the 1.8V plane, current will not flow from the 3.
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® Intel 810E2 Chipset Platform R 3.9. Power Plane Splits Figure 27. Power Plane Split Example pwr_plane_splits 3.10. Thermal Design Power The thermal design power is the estimated maximum possible expected power generated in a component by a realistic application. It is based on extrapolations in both hardware and software technology over the life of the product. It does not represent the expected power generated by a power virus. The thermal design power for the ICH2 is 1.5 W ±15%. 3.11.
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® Intel 810E2 Chipset Platform R 3.11.1. Cabling • Length of cable: Each IDE cable must be equal to or less than 18”. • Capacitance: Less than 30 pF • Placement: A maximum of 6” between drive connectors on the cable. If a single drive is placed on the cable, it should be placed at the end of the cable. If a second drive is placed on the same cable, it should be placed on the connector next closest to the end of the cable (6” away from the end of the cable).
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® Intel 810E2 Chipset Platform R Figure 28. Combination Host-Side / Device-Side IDE Cable Detection IDE drive IDE drive 5V 5V To secondary IDE connector GPIO ICH2 GPIO 10 kΩ 10 kΩ PDIAG# PDIAG# 40-conductor cable PDIAG#/ CBLID# 10 kΩ Resistor required for non-5V-tolerant GPI. 5V To secondary IDE connector 80-conductor GPIO ICH2 GPIO IDE drive IDE drive 5V 10 kΩ 10 kΩ PDIAG# PDIAG# IDE cable PDIAG#/ CBLID# 10 kΩ Open IDE_combo_cable_det Resistor required for non-5V-tolerant GPI.
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® Intel 810E2 Chipset Platform R 3.12.2. Device-Side Cable Detection For platforms that must implement device-side detection only (e.g., NLX platforms), a 0.047-µF capacitor is required on the motherboard as shown in the figure below. This capacitor should not be populated when implementing the recommended combination host-side/device-side cable detection mechanism described previously. Figure 29.
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® Intel 810E2 Chipset Platform R 3.12.3. Primary IDE Connector Requirements Figure 30. Connection Requirements for Primary IDE Connector PCIRST_BUF# 22–47 Ω Reset# PCIRST# * PDD[15:0] PDA[2:0] PDCS1# PDCS3# PDIOR# PDIOW# PDDREQ 3.3 V 4.7 kΩ 3.3 V 8.2–10 kΩ Primary IDE Connector PIORDY IRQ14 PDDACK# GPIOx PDIAG# / CBLID# 10 kΩ (needed only for non-5V-tolerant GPI) ICH2 * Due to ringing, PCIRST# must be buffered. CSEL N.C. Pins 32 & 34 IDE_primary_conn_require NOTES: 1.
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® Intel 810E2 Chipset Platform R 3.12.4. Secondary IDE Connector Requirements Figure 31. Connection Requirements for Secondary IDE Connector PCIRST_BUF# 22–47 Ω Reset# PCIRST# * SDD[15:0] SDA[2:0] SDCS1# SDCS3# SDIOR# SDIOW# SDDREQ 3.3 V 4.7 kΩ 3.3 V 8.2–10 kΩ Secondary IDE Connector SIORDY IRQ15 SDDACK# GPIOy PDIAG# / CBLID# 10 kΩ (needed only for non-5V-tolerant GPI) ICH2 * Due to ringing, PCIRST# must be buffered. CSEL N.C. Pins 32 & 34 IDE_secondary_conn_require NOTES: 1.
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® Intel 810E2 Chipset Platform R 3.13. AC’97 The ICH2 implements an AC’97 2.1-compliant digital controller. Any codec attached to the ICH2 AClink must be AC’97 2.1 compliant, as well. Contact your codec IHV for information on 2.1-compliant products. The AC’97 2.1 specification is available on the Intel website: http://developer.intel.com/pc-supp/platform/ac97/index.htm. The AC-link is a bi-directional, serial PCM digital stream.
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® Intel 810E2 Chipset Platform R Clocking is provided from the primary codec on the link via BITCLK, and it is derived from a 24.576-MHz crystal or oscillator. Refer to the primary codec vendor for crystal or oscillator requirements. BITCLK is a 12.288-MHz clock driven by the primary codec to the digital controller (ICH2) and any other codec present. That clock is used as the timebase for latching and driving data. The ICH2 supports wake-on-ring from S1–S5 via the AC’97 link.
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® Intel 810E2 Chipset Platform R As shown in the following figure, when a single codec is located on the motherboard, the resistor RA and the circuitry (AND and NOT gates) shown inside the dashed box must be implemented on the motherboard. This circuitry is required to disable the motherboard codec when a CNR is installed containing two AC ’97 codecs (or a single AC ’97 codec that must be the primary codec on the AC-Link).
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® Intel 810E2 Chipset Platform R Figure 34. CDC_DN_ENAB# Support Circuitry for Multi-Channel Audio Upgrade Motherboard Primary Audio Codec CNR Board SDATA_IN RESET# Audio Codec RESET# SDATA_IN From AC '97 Controller AC97_RESET# ID0# Vcc RB 100kohms To General Purpose Input To AC '97 Digital Controller CDC_DN_ENAB# RA 10kohms SDATA_IN0 SDATA_IN1 CNR Connector Figure 35 shows the circuitry required on the motherboard to support a two-codec down configuration.
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® Intel 810E2 Chipset Platform R The following figure shows the case of two-codecs down and a dual-codec CNR. In this case, both codecs on the motherboard are disabled (while both on CNR are active) by RA being 10 kΩ and RB being 1 kΩ. Figure 36.
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® Intel 810E2 Chipset Platform R 3.13.1.1. Valid Codec Configurations Table 20. Codec Configurations Valid Codec Configurations Invalid Codec Configurations AC(Primary) MC(Primary) + X(any other type of codec) MC(Primary) AMC(Primary) + AMC(Secondary) AMC(Primary) AMC(Primary) + MC(Secondary) AC(Primary) + MC(Secondary) AC(Primary) + AC(Secondary) AC(Primary) + AMC(Secondary) 3.13.2.
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® Intel 810E2 Chipset Platform R 3.14. CNR The Communication and Networking Riser (CNR) Specification defines a hardware-scalable Original Equipment Manufacturer (OEM) motherboard riser and interface. This interface supports multi-channel audio, a V.90 analog modem, phone-line based networking, and 10/100 Ethernet based networking. The CNR specification defines the interface that should be configured before system shipment.
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® Intel 810E2 Chipset Platform R impedance of both wires, resulting in an individual wire presenting a 45-Ω impedance. The trace impedance can be controlled by carefully selecting the trace width, trace distance from power or ground planes, and physical proximity of nearby traces. • USB data lines must be routed as critical signals. The P+/P- signal pair must be routed together, parallel to each other on the same layer, and not parallel with other non-USB signal traces to minimize crosstalk.
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® Intel 810E2 Chipset Platform R 3.16. ISA Implementations that require ISA support can benefit from the enhancements of the ICH2, while “ISAless” designs are not burdened with the complexity and cost of the ISA subsystem. For information regarding the implementation of an ISA design, contact external suppliers. 3.17. IOAPIC Design Recommendation UP systems not using the IOAPIC should comply with the following recommendations: • On the ICH2:  Tie PICCLK directly to ground.
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® Intel 810E2 Chipset Platform R Figure 39. SMBus/SMLink Interface SPD Data Host Controller and Slave Interface Network Interface Card on PCI Temperature on Thermal Sensor SMBus SMBCLK Microcontroller SMBDATA 82801BA SMLink SMLink0 SMLink1 Wire OR (Optional) 82850 Motherboard LAN Controller smbus-link Note: Intel does not support external access to the ICH2’s integrated LAN controller via the SMLink interface.
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® Intel 810E2 Chipset Platform R 3.19. PCI The ICH2 provides a PCI Bus interface compliant with the PCI Local Bus Specification, Revision 2.2. The implementation is optimized for high-performance data streaming when the ICH2 is acting as either the target or the initiator on the PCI bus. For more information on the PCI Bus interface, refer to the PCI Local Bus Specification, Revision 2.2. The ICH2 supports six PCI Bus masters (excluding the ICH2), by providing six REQ#/GNT# pairs.
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® Intel 810E2 Chipset Platform R 3.20.1. RTC Crystal The ICH2 RTC module requires an external oscillating source of 32.768 kHz connected on the RTCX1 and RTCX2 pins. The following figure documents the external circuitry that comprises the oscillator of the ICH2 RTC. ® Figure 41. External Circuitry for the Intel ICH2 RTC 3.3V VCCSUS VCCRTC 2 1 kΩ 1 µF RTCX2 3 Vbatt 1 kΩ 32768 Hz Xtal R1 10 M Ω RTCX1 4 C1 0.047 uF C3 1 18 pF R2 10 M Ω VBIAS 5 C2 1 18 pF VSSRTC 6 rtc_cir.vsd NOTES: 1.
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® Intel 810E2 Chipset Platform R 3.20.2. External Capacitors To maintain RTC accuracy, the external capacitor C1 must be 0.047 µF, and the external capacitor values (C2 and C3) should be chosen to provide the manufacturer-specified load capacitance (Cload) for the crystal, when combined with the parasitic capacitance of the trace, socket (if used), and package.
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® Intel 810E2 Chipset Platform R Figure 42. Diode Circuit to Connect RTC External Battery VCC3_3SBY 1 kΩ VccRTC 1.0 µF + - RTC_ext_batt_diode_circ A standby power supply should be used in a desktop system, to provide continuous power to the RTC when available, which will significantly increase the RTC battery life and thereby the RTC accuracy. 3.20.5. RTC External RTCRST Circuit ® Figure 43. RTCRST External Circuit for Intel ICH2 RTC VCC3_3SBY Diode / battery circuit 1 kΩ Vcc RTC 1.0 µF 8.
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® Intel 810E2 Chipset Platform R The ICH2 RTC requires some additional external circuitry. The RTCRST# signal is used to reset the RTC well. The external capacitor and the external resistor between RTCRST# and the RTC battery (Vbat) were selected to create a RC time delay such that RTCRST# goes high some time after the battery voltage is valid. The RC time delay should be within the range of 10–20 ms.
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® Intel 810E2 Chipset Platform R Figure 44. RTC Power-well Isolation Control empty MMBT3906 iP/N 101421-602 RSMRST# RSMRST# ICH2 from Glue Chip or other source 10k BAV99 iP/N 305901-001 BAV99 iP/N 305901-001 2.
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® Intel 810E2 Chipset Platform R 3.21. LAN Layout Guidelines The ICH2 provides several options for integrated LAN capability. The platform supports several components depending on the target market. These guidelines use the 82562ET to refer to both the 82562ET and 82562EM. The 82562EM is specified in those cases where there is a difference.
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® Intel 810E2 Chipset Platform R Table 22. LAN Design Guide Section Reference Layout Section Intel® ICH2 – LAN interconnect General routing guidelines Intel® 82562EH A B,C,D Design Guide Section Section 3.21.1 Intel® ICH2 – LAN Interconnect Guidelines Section 3.21.2 General LAN Routing Guidelines and Considerations B Section 3.21.3 Intel® 82562EH Home/PNA* Guidelines Intel 82562ET /82562EM C Section 3.21.
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® Intel 810E2 Chipset Platform R 3.21.1.2. Point-to-Point Interconnect The following guidelines are for a single-solution motherboard. Either 82562EH, 82562ET or CNR is installed. Figure 46. Single-Solution Interconnect L LAN_CLK LAN_RSTSYNC ICH2 Platform LAN Connect (PLC) LAN_RXD[2:0] LAN_TXD[2:0] lan_p2p Table 23. Single-Solution Interconnect Length Requirements Configuration L Intel® 82562EH 4.5” to 10” ® Intel 82562ET 3.5” to 10” CNR 3” to 9” 3.21.1.3.
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® Intel 810E2 Chipset Platform R Table 24. LOM/CNR Length Requirements Configuration Intel® 82562EH A B C 0.5” to 6.0” 4.0” to (10.0” – A) Intel 82562ET 0.5” to 7.0” 3.0” to (10.0” – A) Dual footprint 0.5” to 6.5” 3.5” to (10.0” – A) Intel® 82562ET/EH card* 0.5” to 6.5” ® 2.5” to (9” – A) D 0.5” to 3.0” NOTES: 1. The total trace length should not exceed 13”.
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® Intel 810E2 Chipset Platform R 3.21.1.5. Crosstalk Consideration Noise due to crosstalk must be carefully minimized. Crosstalk is the main cause of timing skews and is the largest part of the tRMATCH skew parameter. 3.21.1.6. Impedances Motherboard impedances should be controlled to minimize the impact of any mismatch between the motherboard and the add-in card. An impedance of 60 Ω ± 15% is strongly recommended. Otherwise, signal integrity requirements may be violated. 3.21.1.7.
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® Intel 810E2 Chipset Platform R Figure 49. Trace Routing 45 degrees Trace 45 degrees Trace Geometry and Length The key factors in controlling trace EMI radiation are the trace length and the ratio of trace width to trace height above the ground plane. To minimize trace inductance, high-speed signals and signal layers close to a ground or power plane should be as short and wide as practical. Ideally, this ratio of trace width to height above the ground plane is between 1:1 and 3:1.
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® Intel 810E2 Chipset Platform R 3.21.2.2. Power and Ground Connections Comply with the following rules and guidelines for power and ground connections: • All VCC pins should be connected to the same power supply. • All VSS pins should be connected to the same ground plane. • Use one decoupling capacitor per power pin for optimized performance. • Place decoupling as close as possible to power pins.
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® Intel 810E2 Chipset Platform R Comply with the following rules to help reduce circuit inductance in both backplanes and motherboards: • Route traces over a continuous plane with no interruptions (i.e., do not route over a split plane). If there are vacant areas on a ground or power plane, avoid routing signals over the vacant area. This will increase inductance and EMI radiation levels. • To reduce coupling, separate noisy digital grounds from analog grounds.
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® Intel 810E2 Chipset Platform R 3.21.2.4. Common Physical Layout Issues Common physical layer design and layout mistakes in LAN on Motherboard designs are as follows: 1. Unequal length of the two traces within a differential pair. Inequalities create common-mode noise and distort transmit or receive waveforms. 2. Lack of symmetry between the two traces within a differential pair.
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® Intel 810E2 Chipset Platform R to ground. Using capacitors with capacitances exceeding a few pF in either of these locations can slow the 100-Mbps rise and fall times so much that they fail the IEEE rise time and fall time specifications. This will cause the return loss to fail at higher frequencies and will degrade the transmit BER performance. Caution should be exercised if a cap is put in either of these locations. If a cap is used, it should almost certainly be less than 22 pF.
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® Intel 810E2 Chipset Platform R 3.21.3.2. ® Guidelines for Intel 82562EH Component Placement Component placement can affect the signal quality, emissions, and temperature of a board design. This section discusses guidelines for component placement. Careful component placement can: • Decrease potential problems directly related to electromagnetic interference (EMI), which could result in failure to meet FCC specifications. • Simplify the task of routing traces.
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® Intel 810E2 Chipset Platform R ® Figure 51. Intel 82562EH Termination A+3.3 V 806 Ω 0.022 µF 1 rx_tx_p T 2 3 51.1 Ω rx_tx_n 0 10 Tip 9 Ring 1 2 3 4 5 6 B6008 Tab 7 Tab 806 Ω 51.1 Ω Line 8 1500 pF 1500 pF 6.8 µH 6.8 µH 1 2 3 4 5 6 Tab 6.8 µH Tab 7 6.8 µH Phone / m odem 8 Shield ground IO_subsys_82562EH_term The filter and magnetics component T1 integrates the required filter network, high-voltage impulse protection, and transformer to support the HomePNA LAN interface.
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® Intel 810E2 Chipset Platform R 3.21.3.5. Critical Dimensions There are three dimensions to consider during layout. Distance ‘B’ from the line RJ11 connector to the magnetics module, distance ‘C’ from the phone RJ11 to the LPF (if implemented), and distance ‘A’ from 82562EH to the magnetics module (see the following figure). Figure 52.
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® Intel 810E2 Chipset Platform R Distance from Intel® 82562EH to Magnetics Module Due to the high speed of signals present, distance ‘A’ between the 82562EH and the magnetic should also be less than 1”, but should be second priority relative to distance from connects to the magnetic module. Generally speaking, any section of trace intended for use with high-speed signals should be subject to proper termination practices.
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® Intel 810E2 Chipset Platform R 3.21.4.2. Crystals and Oscillators To minimize the effects of EMI, clock sources should not be placed near I/O ports or board edges. Radiation from these devices may be coupled onto the I/O ports or out of the system chassis. Crystals should also be kept away from the Ethernet magnetics module to prevent interference with communication. If they exist, the retaining straps of the crystal should be grounded to prevent possible radiation from the crystal case.
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® Intel 810E2 Chipset Platform R 3.21.4.4. Critical Dimensions There are two dimensions to consider during layout. Distance ‘B’ from the line RJ45 connector to the magnetics module and distance ‘A’ from the 82562ET or 82562EM to the magnetics module (see the following figure). Figure 54.
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® Intel 810E2 Chipset Platform R ® Distance from Intel 82562ET to Magnetics Module Distance B should also be designed to be less than 1” between devices. The high-speed nature of the signals propagating through these traces requires that the distance between these components be closely observed. In general, any section of traces intended for use with high-speed signals should be subject to proper termination practices.
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® Intel 810E2 Chipset Platform R Figure 55. Termination Plane TDP N/C TDN RDP RJ-45 RDN Magnetics Module Termination Plane Additional capacitance that may need to be added for EFT testing term_plane 3.21.4.6. Intel® 82562ET/EM Disable Guidelines To disable the 82562ET/EM (82562ET/EM), the device must be isolated (disabled) prior to reset (RSM_PWROK) asserting. Using a GPIO, such as GPO28 to be LAN_Enable (enabled high), LAN will default to enabled on initial power-up and after an AC power loss.
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® Intel 810E2 Chipset Platform R There are four pins which are used to put the 82562ET/EM controller in different operating states: Test_En, Isol_Tck, Isol_Ti, and Isol_Tex. The table below describes the operational/disable features for this design.
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® Intel 810E2 Chipset Platform R Figure 58. Dual-Footprint Analog Interface 82562EH/82562ET Tip TDP TDN RDP Ring Magnetics Module RDN RJ11 82562EH Config. RJ45 82562ET Config. TXP TXN dual_ft_AN_conn The following are additional guidelines for this configuration: • L = 3.5” to 10.0” • Stub < 0.5” • Either 82562EH or 82562ET/82562EM can be installed, but not both. • 82562ET pins 28, 29, and 30 overlap with 82562EH pins 17, 18, and 19. • Overlapping pins are tied to ground.
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® Intel 810E2 Chipset Platform R 3.22. LPC/FWH The following provides general guidelines for compatibility and design recommendations for supporting the FWH flash BIOS device. The majority of the changes will be incorporated in the BIOS. 3.22.1. In-Circuit FWH Programming All cycles destined for the FWH will appear on the PCI. The ICH2 hub interface-to-PCI Bridge puts all processor boot cycles out on the PCI (before sending them out on the FWH interface).
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® Intel 810E2 Chipset Platform R 3.23. FWH Decoupling A 0.1 µF capacitor should be placed between the Vcc supply pins and the Vss ground pins to decouple high frequency noise, which may affect the programmability of the device. Additionally, a 4.7 µF capacitor should be placed between the Vcc supply pins and the Vss ground pin to decouple low frequency noise. The capacitors should be placed no further than 390 mils from the Vcc supply pins. 3.24. Processor PLL Filter Recommendation 3.24.1.
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® Intel 810E2 Chipset Platform R The filter specification is graphically shown in the following figure. Figure 61. Filter Specification 0.2dB 0dB x dB -28dB -34dB DC 1Hz fpeak 1 MHz passband x = 20.log[(Vcc-60mV)/Vcc] 66 MHz fcore high frequency band filter1.vsd NOTES: 1. Diagram not to scale. 2. No specification for frequencies beyond fcore. 3. fpeak, if it exists, should be less than 0.05 MHz. Other requirements: • Filter should support DC current > 30 mA.
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® Intel 810E2 Chipset Platform R 3.24.4. Recommendation for Intel® Platforms The following tables are examples of components that meet Intel’s recommendations, when configured in the topology presented in Figure 60. Table 25. Inductor Part Number Value Tol SRF Rated I DCR TDK MLF2012A4R7KT 4.7 µH 10% 35 MHz 30 mA 0.56 Ω (1 W max) Murata LQG21N4R7K00T1 4.7 µH 10% 47 MHz 30 mA 0.7 Ω (±50%) Murata LQG21C4R7N00 4.7 µH 30% 35 MHz 30 mA 0.3 Ω max Table 26.
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® Intel 810E2 Chipset Platform R Figure 62. Using Discrete R VCC CORE R L <0.1 ohm route PLL1 Discrete Resistor 370-Pin Socket C PLL2 <0.1 ohm route v005 Figure 63. No Discrete R VCC CORE L <0.1 ohm route PLL1 Trace Resistance 370-Pin Socket C PLL2 <0.
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® Intel 810E2 Chipset Platform R 3.24.5. Custom Solutions As long as filter performance as specified in the previous “Filter Specification” figure and other requirements outlined in Section 3.24.1. are satisfied, other solutions are acceptable. Custom solutions should be simulated against a standard reference core model, which is shown in the figure below. Figure 64. Core Reference Model PLL1 Processor 0.1 ohm 120pF PLL2 1K ohm 0.1 ohm NOTES: 1. 0.1 Ω resistors represent package routing1. 2.
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® Intel 810E2 Chipset Platform R 3.25. RAMDAC/Display Interface The following figure shows the interface of the RAMDAC analog current outputs with the display. Each DAC output is doubly-terminated with a 75-Ω resistance; one 75-Ω resistance from the DAC output to the board ground and the other termination resistance exists within the display. The equivalent DC resistance at the output of each DAC output is 37.5 Ω.
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® Intel 810E2 Chipset Platform R In addition to the termination resistance and LC pi-filter, there are protection diodes connected to the RAMDAC outputs to help prevent latch-up. The protection diodes must be connected to the same power supply rails as the RAMDAC. An LC filter is recommended to connect the segmented analog 1.8V power plane of the RAMDAC to the 1.8V board power plane. The LC filter is recommended to be designed for a cut-off frequency of 100 kHz. 3.25.1.
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® Intel 810E2 Chipset Platform R Figure 66. RAMDAC Component and Routing Guidelines Place LC filter components & high frequency de-coupling capacitors as close to the power pins as possible. Analog Power Plane Lf 1.8V 1.8V Board Power Plane 1.8V Board Power Plane Cf LC Filter Place the pi-Filter in close proximity to the VGA connector. 1.8V Board Power Plane Graphics Chip 75 Ω Routes FB D1 VCCDACA1/ VCCDACA2 VCCDA 37.5 Ω Route RED Red Route C1 Rt D2 RAMDAC C2 pi Filter 1.
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® Intel 810E2 Chipset Platform R The following figure shows the recommended reference resistor placement and connections. Figure 67.
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® Intel 810E2 Chipset Platform R Figure 68. Recommended LC Filter Connection Board Power Plane R L DPLL Analog Power C Board Ground Plane VCCDA RAMDAC Analog Power VCCDACA1 VCCDACA2 Display PLL and RAMDAC VSSDA VSSDACA Board Ground Plane lc_filter.vsd The resistance from the inductor to the board 1.8V power plane represents the total resistance from the board power plane to the filter capacitor.
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® Intel 810E2 Chipset Platform R the filter characteristics. This resistance includes the routing resistance from the board power plane connection to the filter inductor, the filter inductor parasitic resistance, the routing from the filter inductor to the filter capacitor, and resistance of the associated vias. Part of this resistance can be a physical resistor. A physical resistor may not be needed depending on the resistance of the inductor and the routing/via resistance.
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® Intel 810E2 Chipset Platform R Table 29. Additional DPLL LC Filter Component Example Component Manufacturer Part No. Description Capacitor KEMET T495D336MD16AS 33 µF ±20%, 16VDC, ESR=0.225 Ω @ 100 kHz, ESL=2.5 nH Inductor muRATA LQG21NR10K10 100 nH ±10%, 250 mA, Max dc resistance = 0.26 Ω, size=0805, magnetically shielded As an example, is a Bode plot showing the frequency response using the capacitor and inductor values shown in Table 30.
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® Intel 810E2 Chipset Platform R Table 30. Resistance Values for Frequency Response Curves Curve RTRACE + RDISCRETE RIND 0 2.2 Ω 0.8 Ω 1 2.2 Ω 0.4 Ω 2 0Ω 0.4 Ω 3 0Ω 0.8 Ω As series resistance (RTRACE + RDISCRETE + RIND) increases, the filter response (i.e., attenuation in PLL bandwidth) improves. There is a limit of 3.3 Ω total series resistance of the filter to limit DC voltage drop.
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® Intel 810E2 Chipset Platform R 4. Advanced System Bus Design This chapter discusses more detail about the methodology used to develop the guidelines. Section 4.1 specific system guidelines. This is a step-by-step methodology that Intel has successfully used to design high performance desktop systems. Section 4.2 introduces the theories that are applicable to this layout guideline. Section 4.3 contains more details and insights. The items in Section 4.
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® Intel 810E2 Chipset Platform R 4.1.1. Initial Timing Analysis Perform an initial timing analysis of the system using the Setup Time and Hold Time equations shown below. These equations are the basis for timing analysis. To complete the initial timing analysis, values for clock skew and clock jitter are needed, along with the component specifications.
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® Intel 810E2 Chipset Platform R There are multiple cases to consider. Note that while the same trace connects two components, component A and component B, the minimum and maximum flight time requirements for component A driving component B as well as component B driving component A must be met.
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® Intel 810E2 Chipset Platform R Table 32 and Table 33 are derived assuming: • CLKSKEW = 0.2 ns (Note: Assumes clock driver pin-to-pin skew is reduced to 50 ps by tying two host clock outputs together (“ganging”) at clock driver output pins, and the PCB clock routing skew is 150 ps. System timing budget must assume 0.175 ns of clock driver skew if outputs are not tied together and a clock driver that meets the CK98 clock driver specification is being used.) • CLKJITTER = 0.
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® Intel 810E2 Chipset Platform R 4.1.2. Determine General Topology, Layout, and Routing Desired After calculating the timing budget, determine the approximate location of the processor and the chipset on the baseboard. 4.1.3. Pre-Layout Simulation 4.1.3.1. Methodology Analog simulations are recommended for high-speed system bus designs. Start simulations prior to layout.
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® Intel 810E2 Chipset Platform R 4.1.3.3. Monte Carlo Analysis Perform a Monte Carlo analysis to refine the passing solution space region. A Monte Carlo analysis involves randomly varying parameters (independent of one another) over their tolerance range. This analysis intends to ensure that no regions of failing flight time and signal quality exists between the extreme corner cases run in pre-layout simulations.
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® Intel 810E2 Chipset Platform R The transmission line package models must be inserted between the output of the buffer and the net it is driving. Likewise, the package model must also be placed between a net and the input of a receiver model. Editing the simulator’s net description or topology file generally does this. Intel has found wide variation in noise margins when varying the stub impedance and the PCB’s Z0 and S0.
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® Intel 810E2 Chipset Platform R Table 34 contains the trace width:space ratios assumed for this topology. The crosstalk cases considered in this guideline involve three types: Intragroup AGTL+, Intergroup AGTL+, and AGTL+ to nonAGTL+. Intra-group AGTL+ crosstalk involves interference between AGTL+ signals within the same group (See Section 4.3). Intergroup AGTL+ crosstalk involves interference from AGTL+ signals in a particular group to AGTL+ signals in a different group.
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® Intel 810E2 Chipset Platform R 4.1.5.1. Intersymbol Interference Intersymbol Interference (ISI) refers to the distortion or change in the waveform shape caused by the voltage and transient energy on the network when the driver begins its next transition. Intersymbol Interference (ISI) occurs when transitions in the current cycle interfere with transitions in subsequent cycles. ISI can occur when the line is driven high, low, and then high in consecutive cycles (the opposite case is also valid).
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® Intel 810E2 Chipset Platform R 4.1.6.2. Flight Time Simulation As defined in Chapter 1, flight time is the time difference between a signal crossing VREF at the input pin of the receiver, and the output pin of the driver crossing VREF were it driving a test load. The timings in the tables and topologies discussed in this guideline assume the actual system load is 50 Ω and is equal to the test load.
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® Intel 810E2 Chipset Platform R 4.1.6.3. Flight Time Hardware Validation When a measurement is made on the actual system, TCO and flight time do not need TREF correction since these are the actual numbers. These measurements include all of the effects pertaining to the driversystem interface and the same is true for the TCO. Therefore the addition of the measured TCO and the measured flight time must be equal to the valid delay calculated above.
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® Intel 810E2 Chipset Platform R 4.2.3. Crosstalk Theory AGTL+ signals swing across a smaller voltage range and have a correspondingly smaller noise margin than technologies that have traditionally been used in personal computer designs. This requires that designers using AGTL+ be more aware of crosstalk than they may have been in past designs. Crosstalk is caused through capacitive and inductive coupling between networks. Crosstalk appears as both backward crosstalk and as forward crosstalk.
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® Intel 810E2 Chipset Platform R Additional aggressors are possible in the z-direction, if adjacent signal layers are not routed in mutually perpendicular directions. Because crosstalk-coupling coefficients decrease rapidly with increasing separation, it is rarely necessary to consider aggressors that are at least five line widths separated from the victim. The maximum crosstalk occurs when all the aggressors are switching in the same direction at the same time.
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® Intel 810E2 Chipset Platform R Intrinsic Impedance L0 Z0 = C0 ( Ω) Stripline Intrinsic Propagation Speed S0_ STRIPLINE = 1017 . * εr (ns/ft) Microstrip Intrinsic Propagation Speed S0_ MICROSTRIP = 1017 . * 0.475 * ε r + 0.
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® Intel 810E2 Chipset Platform R 4.3.2. Effective Impedance and Tolerance/Variation The impedance of the PCB needs to be controlled when the PCB is fabricated. The method of specifying control of the impedance needs to be determined to best suit each situation.
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® Intel 810E2 Chipset Platform R When it is not possible to route the entire AGTL+ signal on a single VSS referenced layer, there are methods to reduce the effects of layer switches. The best alternative is to allow the signals to change layers while staying referenced to the same plane (see Figure 74). Figure 75 shows another method of minimizing layer switch discontinuities, but may be less effective than Figure 74. In this case, the signal still references the same type of reference plane (ground).
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® Intel 810E2 Chipset Platform R Figure 77. One Layer with Multiple Reference Planes Signal Layer A Ground Power 1lay_Mult_refplane.vsd 4.3.3.2. High Frequency Decoupling This section contains several high frequency decoupling recommendations that will improve the return path for an AGTL+ signal. These design recommendations will likely reduce the amount of SSO effects.
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® Intel 810E2 Chipset Platform R 4.3.4. Clock Routing Analog simulations are required to ensure clock net signal quality and skew is acceptable. The system clock skew must be kept to a minimum (The calculations and simulations for the example topology given in this document have a total clock skew of 200 ps and 150 ps of clock jitter). For a given design, the clock distribution system, including the clock components, must be evaluated to ensure these same values are valid assumptions.
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® Intel 810E2 Chipset Platform R 4.4.1. VREF Guardband To account for noise sources that may affect the way an AGTL+ signal becomes valid at a receiver, VREF is shifted by ∆VREF for measuring minimum and maximum flight times. The VREF Guardband region is bounded by VREF - ∆VREF and VREF + ∆VREF. ∆VREF has a value of 100 mV, which accounts for the following noise sources: • Motherboard coupling • VTT noise • VREF noise 4.4.2.
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® Intel 810E2 Chipset Platform R 4.4.4. Flight Time Definition and Measurement Timing measurements consist of minimum and maximum flight times to take into account that devices can turn on or off anywhere in a VREF Guardband region. This region is bounded by VREF - ∆VREF and VREF + ∆VREF. The minimum flight time for a rising edge is measured from the time the driver crosses VREF when terminated to a test load, to the time when the signal first crosses VREF - ∆VREF at the receiver (see the figure below).
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® Intel 810E2 Chipset Platform R 5. Clocking 5.1. Clock Generation There is only one clock generator component required in an 810E2 chipset system. The CK810E clock chip is pin compatible with the CK810 clock chip, which comes in a single 56-pin SSOP package. There is one pin function change in the CK810E relative to the CK810, the REFCLK Reset Strap: Table 35. REFCLK Reset Strap for CK810 vs.
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® Intel 810E2 Chipset Platform R Features (56 Pin SSOP Package) • 3 copies of processor clock 66/100/133 MHz (2.5V) (Processor, GMCH, ITP) • 9 copies of 100 MHz (all the time) SDRAM clock (3.3V) (SDRAM[0:7], DClk) • 8 copies of PCI clock (33 MHz ) (3.3V) • 2 copies of APIC clock @16.67 MHz or 33 MHz, synchronous to processor clock (2.5V) • 2 copy of 48 MHz clock (3.3V) [Non SSC] • 2 copies of 3V66 MHz clock (3.3V) • 1 copy of REF clock @14.31818 MHz (3.
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® Intel 810E2 Chipset Platform R 5.2. Clock Architecture ® Figure 80. Intel 810E2 Chipset Clock Architecture Processor ITP CPU_2_ITP APIC_0 2.5V CPU_1 CPU_0 52 55 50 49 Clock Synthesizer PW RDW N SEL1 SEL0 SDATA SCLK SDRAM0 SDRAM1 SDRAM2 SDRAM3 SDRAM4 SDRAM5 SDRAM6 SDRAM7 3.3V DCLK 3V66_0 USB_0 32 29 28 30 Data 31 46 M ain Mem ory 2 DIM MS Address 45 GM CH 43 Control 42 40 39 37 36 34 7 25 Dot Clock 14.3118 MHz 3V66_1 REF PCIO/ICH USB1 2.5V APIC1 PCI_1 3.
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® Intel 810E2 Chipset Platform R 5.3. Clock Routing Guidelines The following table shows the group skew and jitter limits. Table 37. Group Skew and Jitter Limits at the Pins of the Clock Chip Signal Group Pin-Pin Skew Cycle-Cycle Jitter Nominal Vdd Skew, Jitter Measure Point Processor 175 pS 250 pS 2.5V 1.25V SDRAM 250 pS 250 pS 3.3V 1.50V APIC 250 pS 500 pS 2.5V 1.25V 48 MHz 250 pS 500 pS 3.3V 1.50V 3V66 175 pS 500 pS 3.3V 1.50V PCI 500 pS 500 pS 3.3V 1.
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® Intel 810E2 Chipset Platform R Table 39. Layout Dimensions Group Receiver Resistor Cap Topology A B C D MCLK DIMM 22 Ω N/A Layout 1 0.5” X N/A N/A Processor Intel® Pentium® III FC-PGA Processor 100/133 MHz Segment C => Pentium III FCPGA Processor 33 Ω N/A Layout 5 0.1” 0.5” X+4.8" X+7.1” Processor Intel® Celeron® Processor 66/100 MHz Segment C => Celeron Processor Socket 33 Ω N/A Layout 5 0.1” 0.5” X+5.4" X+7.1” DCLK GMCH 33 Ω 22 pF Layout 3 0.5” X+3.2” 0.
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® Intel 810E2 Chipset Platform R Figure 81.
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® Intel 810E2 Chipset Platform R 5.4. Capacitor Sites Intel recommends 0603 package capacitor sites placed as close as possible to the clock input receivers for AC tuning for the following signal groups: • GMCH • Processor • SDRAM/DCLK • 3V66 • 3V66 to the ICH2 Figure 82.
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® Intel 810E2 Chipset Platform R 5.5. Clock Power Decoupling Guidelines Several general layout guidelines should be followed when laying out the power planes for the CK810E clock generator. • Isolate power planes to the each of the clock groups. • Place local decoupling as close to power pins as possible and connect with short, wide traces and copper. • Connect pins to appropriate power plane with power vias (larger than signal vias).
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® Intel 810E2 Chipset Platform R Figure 83.
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® Intel 810E2 Chipset Platform R 5.6. Clock Skew Requirements To ensure correct system functionality, certain clocks must maintain a skew relationship to other clocks as summarized in the following section. 5.6.1. IntraGroup Skew Limits Clocks within each group must maintain appropriate skew relationship to each other. These requirements are summarized in the following table. Table 40.
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® Intel 810E2 Chipset Platform R 6. Power Delivery The following figure shows the power delivery architecture for an example 810E2 chipset platform. This power delivery architecture supports the “Instantly Available PC Design Guidelines” via the suspend-toRAM (STR) state. During STR, only the necessary devices are powered. These devices include: main memory, the ICH2 resume well, PCI wake devices (via 3.3 Vaux), AC’97, and optionally USB. (USB can be powered only if sufficient standby power is available.
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® Intel 810E2 Chipset Platform R Figure 84. Power Delivery Map Fan Processor Intel® 810E2 Chipset Universal Socket 370 Platform Power Map Core: VCC_VID: 1.5V1 28.5 A S0, S1 VRM8.5 ATX P/S with 720 mA 5 VSB ± 5% 5V ± 5% 3.3 V ± 5% Serial ports Core: VCC_VID: 1.75V1 22.0 A S0, S1 Serial xceivers-12: 12 V ± 1.2 V 22 mA S0, S1 VTT: 1.25V1 2.7A S0, S1 12 V -12 V ± 5% ± 10% VTT regulator Serial xceivers-N12: -12 V ± 1.2 V 28 mA S0, S1 VTT: 1.5V1 2.7A S0, S1 Serial xceivers-5: 5 V ± 0.
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® Intel 810E2 Chipset Platform R Figure 85. G3-S0 Transistion Vcc3.3sus t1 RSMRST# t2 t3 SLP_S3# t4 SLP_S5# t5 SUS_STAT# t6 Vcc3.
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® Intel 810E2 Chipset Platform R Figure 86. S0-S3-S0 Transition Vcc3.3sus RSMRST# t24 STPCLK# Stop grant cycle t18 t7 CPUSLP# Go_C3 from ICH Ack_C3 from GMCH DRAM DRAM in STR (CKE low) DRAM active DRAM active t19 SUS_STAT# t20 t11 PCIRST# t12 Cycle 1 from GMCH Cycle 1 from ICH2 t13 Cycle 2 from GMCH Cycle 2 from ICH2 t17 CPURST# t21 t23 SLP_S3# SLP_S5# t8 PWROK t22 Vcc3.
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® Intel 810E2 Chipset Platform R Figure 87. S0-S5-S0 Transition Vcc3.3sus RSMRST# t24 STPCLK# Stop grant cycle t18 t7 CPUSLP# Go_C3 from ICH Ack_C3 from GMCH DRAM DRAM in STR (CKE low) DRAM active DRAM active t19 SUS_STAT# t20 t11 PCIRST# t12 Cycle 1 from GMCH Cycle 1 from ICH2 t13 Cycle 2 from GMCH Cycle 2 from ICH2 t17 CPURST# t21 t23 SLP_S3# t25 t26 SLP_S5# t8 PWROK t22 Vcc3.
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® Intel 810E2 Chipset Platform R Table 41. Power Sequencing Timing Definitions Symbol 148 Parameter Min. Max. Units 1 25 ms 50 ns t1 VccSUS good to RSMRST# inactive t2 VccSUS good to SLP_S3#, SLP_S5#, and PCIRST# active t3 RSMRST# inactive to SLP_S3# inactive 1 4 RTC clocks t4 RSMRST# inactive to SLP_S5# inactive 1 4 RTC clocks t5 RSMRST# inactive to SUS_STAT# inactive 1 4 RTC clocks t6 SLP_S3#, SLP_S5#, SUS_STAT# inactive to Vcc3.3core good * * t7 Vcc3.
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® Intel 810E2 Chipset Platform R 6.2. Pull-up and Pull-down Resistor Values The pull-up and pull-down values are system dependent.
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® Intel 810E2 Chipset Platform R 6.3. ATX Power Supply PWRGOOD Requirements The PWROK signal must be glitch free for proper power management operation. The ICH2 sets the PWROK_FLR bit (ICH2 GEN_PMCON_2, General PM Configuration 2 Register, PM-dev31: function 0, bit 0, at offset A2h). If this bit is set upon resume from S3 power-down, the system will reboot and control of the system will not be given to the program running when entering the S3 state.
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® Intel 810E2 Chipset Platform R 6.4.1. Power Button Implementation The following items should be considered when implementing a power management model for a desktop system. The power states are as follows: S1 – Stop Grant – (processor context not lost) S3 – STR (Suspend to RAM) S4 – STD (Suspend to Disk) S5 – Soft-off • Wake: Pressing the power button wakes the computer from S1–S5.
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® Intel 810E2 Chipset Platform R 6.4.2. 1.8V / 3.3V Power Sequencing The ICH2 has two pairs of associated 1.8V and 3.3V supplies. These are (Vcc1_8, Vcc3_3) and (VccSus1_8, VccSus3_3). These pairs are assumed to power up and power down together. The difference between the two associated supplies must never be greater than 2.0V. The 1.8V supply may come up before the 3.3V supply without violating this rule (though this is generally not practical in a desktop environment, since the 1.
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® Intel 810E2 Chipset Platform R If one of these signals goes high while one of its associated power planes is active and the other is not, a leakage path will exist between the active and inactive power wells. This could result in high, possibly damaging, internal currents. 6.4.3. 3.3V / V5REF Sequencing V5REF is the reference voltage for 5V tolerance on inputs to the ICH2. V5REF must be powered up before Vcc3_3, or after Vcc3_3 within .7V.
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® Intel 810E2 Chipset Platform R 6.4.4. GMCH Decoupling Guidelines GMCH Vsus 3.3V (3.3V Standby) Power Plane Decoupling The use of top-side (component side) capacitors near the GMCH (as shown in the following “GMCH Power Plane Decoupling” figure) as the only means of decoupling the VSUS_3.3V power plane may be insufficient to meet the 3.3V droop specification or to attenuate noise. In some cases bottom-side (solder side) capacitors (connected at three to four of the VSUS_3.
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® Intel 810E2 Chipset Platform R Figure 91. GMCH Power Plane Decoupling 6.4.5. Ground Flood Planes To further decouple the 82810E GMCH and provide a solid current return path for the system memory interface signals, it is recommended that 4-layer boards (signal-power-ground-signal) be designed with a topside (device side) ground flood plane under the GMCH. This topside copper flood plane under the center of the GMCH creates a parallel plate capacitor between the power layer and GND.
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® Intel 810E2 Chipset Platform R 6.5. Power_Supply PS_ON Considerations If a pulse on SLP_S3# or SLP_S5# is short enough (~ 10-100mS) such that PS_ON is driven active during the exponential decay of the power rails, a few power supplies may not be designed to handle this short pulse condition. In this case, the power supply will not respond to this event and never power back up. These power supplies would need to be unplugged and re-plugged to bring the system back up.
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® Intel 810E2 Chipset Platform R 7. 7.1. Design Checklist Design Review Checklist This checklist highlights design considerations that should be reviewed prior to manufacturing a motherboard that implements an 810E2 chipset. This is not a complete list and does not guarantee that a design will function properly. Beyond the items contained in the following text, refer to the most recent version of the Design Guide for more detailed instructions on designing a motherboard. 7.1.1.
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® Intel 810E2 Chipset Platform R Table 42. AGTL+ Connectivity Checklist for 370-Pin Socket Processors Processor Pin I/O Recommendations A[35:3]# 1 I/O Connect A[31:3]# to GMCH. Leave A[35:32]# as No Connect (not supported by chipset). ADS# 1 I/O Connect to GMCH. AERR# I/O Leave as No Connect (not supported by chipset). AP[1:0]# I/O Leave as No Connect (not supported by chipset). BERR# I/O Leave as No Connect (not supported by chipset).
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® Intel 810E2 Chipset Platform R Table 43. CMOS Connectivity Checklist for 370-Pin Socket Processors Processor Pin I/O Recommendations A20M# I Connect to ICH2. FERR# O 150 Ω pull-up resistor to VCCCMOS / Connect to ICH2. FLUSH# I 150 Ω pull-up resistor to VCCCMOS (not used by chipset). IERR# O 150 Ω pull-up resistor to VCCCMOS if tied to custom logic or leave as No Connect (not used by chipset). IGNNE# I Connect to ICH2. INIT# I Connect to ICH2 & FWH Flash BIOS.
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® Intel 810E2 Chipset Platform R Table 45. Miscellaneous Checklist for 370-Pin Socket Processors Processor Pin I/O Recommendations BCLK I Connect to clock generator / 22–33 Ω series resistor (though OEM needs to simulate based on driver characteristics). To reduce pin-to-pin skew, tie host clock outputs together at the clock driver then route to the GMCH and processor. BSEL0 I/O Case 1, 66/100/133 MHz support: 1 kΩ pull-up resistor to 3.
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® Intel 810E2 Chipset Platform R Processor Pin VREF[7:0] I/O I Recommendations Connect to Vref voltage divider made up of 75 and 150 Ω 1% resistors connected to Vtt. Decoupling Guidelines: 4 ea. (min) 0.1 µF in 0603 package placed within 500 mils of VREF pins. VTT I Connect AH20, AK16, AL13, AL21, AN11, AN15, and G35 to 1.5V regulator. Provide high and low frequency decoupling. Decoupling Guidelines: 19 ea (min) 0.
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® Intel 810E2 Chipset Platform R Checklist Line Items LMD[27:31] Reset strapping options: Comments Strapping options: For a “1”, use a 10 kΩ (approximate) pull-up resistor to 3.3V; a “0” is default (due to internal pull-down resistors).
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® Intel 810E2 Chipset Platform R 7.2. Intel® ICH2 Checklist 7.2.1. PCI Interface Checklist Items Recommendations All All inputs to the ICH2 must not be left floating. Many GPIO signals are fixed inputs that must be pulled up to different sources. See GPIO section for recommendations. PERR#, SERR# PLOCK#, STOP# DEVSEL#, TRDY# IRDY#, FRAME# REQ#[0:4], GPIO[0:1], THRM# These signals require a pull-up resistor. Recommend an 8.2 kΩ pull-up resistor to VCC3.3 or a 2.7 kΩ pull-up resistor to VCC5.
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® Intel 810E2 Chipset Platform R Checklist Items Comments 5 Max mismatch between the length of a clock trace and the length of any data trace is 0.5 inches (clock must be longest trace) To meet timing and signal quality requirements. 6 Maintain constant symmetry and spacing between the traces within a differential pair out of the LAN phy. To meet timing and signal quality requirements. 7 Keep the total length of each differential pair under 4 inches.
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® Intel 810E2 Chipset Platform R Checklist Items 23 Recommendations Comments Connect to LAN_CLK on Platform LAN Connect Device. LAN_CLK 24 LAN_RXD[2:0] 25 Connect to LAN_RXD on Platform LAN Connect Device. ICH2 contains integrated 9 kΩ pull-up resistors on interface. Connect to LAN_TXD on Platform LAN Connect Device. LAN_TXD[2:0] LAN_RSTSYNC NOTES: 1. LAN connect interface can be left NC if not used. Input buffers internally terminated. 2.
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® Intel 810E2 Chipset Platform R Checklist Items PIRQ[G:F]#/ GPIO[4:3] Recommendations These signals require a pull-up resistor. Recommend a 2.7 kΩ pull-up resistor to VCC5 or 8.2 kΩ to VCC3.3. In Non-APIC Mode the PIRQx# signals can be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as described in the Interrupt Steering section. Each PIRQx# line has a separate Route Control Register.
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® Intel 810E2 Chipset Platform R 7.2.8. USB Checklist Items USBP[3:0]P Recommendations See Figure 92 for circuitry needed on each differential Pair. USBP[3:0]N VCC USB (Cable power) It should be powered from the 5V core instead of the 5V standby, unless adequate standby power is available. Voltage drop considerations The resistive component of the fuses, ferrite beads and traces must be considered when choosing components, and power and GND trace widths.
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® Intel 810E2 Chipset Platform R 7.2.9. Power Management Checklist Items Recommendations THRM# Connect to temperature Sensor. Pull-up if not used. SLP_S3# No pull-up/down resistors needed. Signals driven by ICH2. SLP_S5# PWROK This signal should be connected to power monitoring logic, and should go high no sooner than 10 ms after both Vcc3_3 and Vcc1_8 have reached their nominal voltages PWRBTN# This signal has an integrated pull-up of 24K. RI# RI# does not have an internal pull-up.
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® Intel 810E2 Chipset Platform R 7.2.11. System Management Checklist Items SMBDATA SMBCLK Recommendations Requires external pull-up resistors. See SMBus Architecture and Design Consideration section to determine the appropriate power well to use to tie the pull-up resistors. (Core well, suspend well, or a combination.) Value of pull-up resistors determined by line load. Typical value used is 8.2 kΩ.
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® Intel 810E2 Chipset Platform R 7.2.14. AC’97 Checklist Items AC_BITCLK Recommendations No extra pull-down resistors required. When nothing is connected to the link, BIOS must set a shut off bit for the internal keeper resistors to be enabled. At that point, you do not need pull-ups/pull-downs on any of the link signals. AC_SYNC No extra pull-down resistors required. Some implementations add termination for signal integrity. Platform specific. AC_SDOUT Requires a jumper to 8.
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® Intel 810E2 Chipset Platform R Figure 93. SPKR Circuitry ICH2 3.3V Integrated Pull-up 18 kΩ - 42 kΩ Stuff jumper to disable time-out feature. Effective Impedence due to speaker and codec circuit. Reff > 50 kΩ R < 7.
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® Intel 810E2 Chipset Platform R 7.2.16. Power Checklist Items Recommendations V_CPU_IO[1:0] The power pins should be connected to the proper power plane for the processor 's CMOS Compatibility Signals. Use one 0.1 µF decoupling cap. VccRTC No clear CMOS jumper on VccRTC. Use a jumper on RTCRST# or a GPI, or use a safemode strapping for Clear CMOS Vcc3.3 Requires six 0.1 µF decoupling capacitors VccSus3.3 Requires one 0.1 µF decoupling capacitor. Vcc1.8 Requires two 0.
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® Intel 810E2 Chipset Platform R 7.2.17. IDE Checklist Checklist Items PDD[15:0], SDD[15:0] Recommendations No extra series termination resistors or other pull-ups/pull-downs are required. These signals have integrated series resistors. NOTE: Simulation data indicates that the integrated series termination resistors can range from 31 Ω to 43 Ω. PDD7/SDD7 does not require a 10 kΩ pull-down resistor. Refer to ATA ATAPI-4 specification.
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® Intel 810E2 Chipset Platform R Figure 95. Host/Device Side Detection Circuitry IDE drive IDE drive 5V 5V To secondary IDE connector GPIO ICH2 GPIO 10 kΩ 10 kΩ PDIAG# PDIAG# 40-conductor cable PDIAG#/ CBLID# 10 kΩ IDE drive IDE drive 80-conductor GPIO ICH2 GPIO 5V 5V To secondary IDE connector 10 kΩ 10 kΩ PDIAG# PDIAG# IDE cable PDIAG#/ CBLID# 10 kΩ Open IDE_combo_cable_det Figure 96.
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® Intel 810E2 Chipset Platform R 7.3. LPC Checklist Checklist Items Recommendations RCIN# Pull up through 8.2-kΩ resistor to Vcc3_3. LPC_PME# Pull up through 8.2-kΩ resistor to Vcc3_3. Do not connect LPC PME# to PCI PME#. If the design requires the Super I/O to support wake from any suspend state, connect Super I/O LPC_PME# to a resume well GPI on the ICH2. LPC_SMI# Pull up through 8.2-kΩ resistor to Vcc3_3. This signal can be connected to any ICH2 GPI.
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® Intel 810E2 Chipset Platform R 7.4. System Checklist Checklist Items Recommendations KEYLOCK# Pull up through 10-kΩ resistor to Vcc3_3. PBTN_IN Connects to PBSwitch and PBin. PWRLED Pull up through a 220-Ω resistor to Vcc5. R_IRTX Signal IRTX after it is pulled down through 4.7-kΩ resistor to GND and passes through 82-Ω resistor. IRRX Pull up to 100-kΩ resistor to Vcc3_3. When signal is input for SI/O decouple through 470-pF capacitor to GND IRTX Pull down through 4.7 kΩ to GND.
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® Intel 810E2 Chipset Platform R 7.6. Clock Synthesizer Checklist Checklist Items Recommendations REFCLK Connects to R-RefCLK, USB_CLK, SIO_CLK14, and ICHCLK14. ICH_3V66/3V66_0, DOTCLK Passes through 33-Ω resistor. When signal is input for ICH2, it is pulled down through a 18-pF capacitor to GND. DCLK/DCLK_WR Passes through 33-Ω resistor. When signal is input for GMCH, it is pulled down through a 22-pF capacitor to GND. CPUHCLK/CPU_0_1 Passes through 33-Ω resistor.
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® Intel 810E2 Chipset Platform R 7.7. ITP Probe Checklist Checklist Items 7.8. R_TCK, TCK R_TMS, TMS Connect to 370-Pin socket through 47-Ω resistor and pull up to VCMOS. ITPRDY#, R_ITPRDY# Connect to 370-Pin socket through 243-Ω resistor. TDI Pull up through 330-Ω resistor to VCMOS. TDO Pull up through 150-Ω resistor to VCMOS. PLL1 See Design Guide. PLL2 See Design Guide.
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® Intel 810E2 Chipset Platform R 8. Flexible Motherboard Guidelines 8.1. Flexible Processor Guidelines 8.1.1. Flexible System Design DC Guidelines The processor DC guidelines for flexible system designed in this section is defined at the processor pin. Table 49 lists the guidelines for future 1.5V processors and Table 50 lists the guidelines for future 2.0V processors. Specifications are valid only while meeting specifications for case temperature, clock frequency, and input voltages.
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® Intel 810E2 Chipset Platform R Table 50. Flexible Processor Voltage and Current Guidelines for 2.0 V Processors Symbol Parameter Min VccCORE VCC for processor core Baseboard Tolerance, Static processor core voltage static tolerance at processor pins 0.089 Baseboard Tolerance, Transient processor core voltage transient tolerance level at processor pins 0.144 ICCCORE Typ Max 2.00 1 Unit Notes V 1, 3 0.100 V 2, 3 0.144 V 2, 3 ICC for processor core 15.
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® Intel 810E2 Chipset Platform R 8.1.2. System Bus AC Guidelines Table 51 and Table 52 contain 66 MHz and 100 MHz system bus AC Guidelines defined at the processor pins. For 133 MHz see the Intel Pentium III processor PGA 370 Socket datasheet. Table 51 contains the BCLK guidelines and Table 52 contains the AGTL+ system bus guidelines. Processor System Bus AC Specifications for the AGTL+ Signal Group at the processor pins for 100 MHz are equivalent to 66 MHz.
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® Intel 810E2 Chipset Platform R Figure 97. BCLK Waveform th tr 2.0V CLK 1.25V 0.5V tf tl tp Tr Tf Th Tl Tp = T5 (Rise Time) = T6 (Fall Time) = T3 (High Time) = T4 (Low Time) = T1 (BLCK Period) 761a Table 52. Processor System Bus AC Guidelines (AGTL+ Signal Group) at the Processor 1, 2, 3, 4 Pins T# Parameter Min Max Unit Figure Notes T7: AGTL+ Output Valid Delay 0.30 4.43 ns Figure 98 5 T8: AGTL+ Input Setup Time 1.75 ns Figure 99 5, 6, 7, 8 T9: AGTL+ Input Hold Time 0.
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® Intel 810E2 Chipset Platform R Figure 98. Processor System Bus Valid Delay Timings CLK Tx Signal Tx V Valid Valid Tpw Tx = T7, T11, T29 (Valid Delay) Tpw = T14, T15 (Pulse Wdith) V = 1.0V for GTL+ signal group; 1.25V for CMOS, APIC and JTAG signal groups 000762b Figure 99. Processor System Bus Setup and Hold Timings CLK Ts Signal Th V Valid Ts = T8, T12, T27 (Setup Time) Th = T9, T13, T28 (Hold Time) V = 1.0V for GTL+ signal group; 1.25V for CMOS, APIC and JTAG signal groups Figure 100.
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® Intel 810E2 Chipset Platform R 8.1.3. Thermal Guidelines The following table provides the recommended thermal design power dissipation for use in designing a flexible system board. The processor’s heatslug is the attach location for all thermal solutions. The maximum and minimum case temperatures are specified in the following table. A thermal solution should be designed to ensure the temperature of the case never exceeds these specifications. ® ® Table 53.
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® Intel 810E2 Chipset Platform R 9. Third-Party Vendor Information This design guide has been compiled to give an overview of important design considerations while providing sources for additional information. This chapter includes information regarding various thirdparty vendors who provide products to support the 810E2 chipset. The list of vendors can be used as a starting point for the designer.
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® Intel 810E2 Chipset Platform R Table 58. Flat Panel Vendors Contact Silicon Images Inc John Nelson Phone 408-873-3111 Table 59. AC’97 Vendors Contact Phone Analog Devices Dave Babicz 781-461-3237 AKM George Hill 408-436-8580 Cirrus Logic (Crystal) David Crowell 512-912-3587 Creative Technologies Ltd./ Ensoniq Corp. Steve Erickson 408-428-6600 x6945 Diamond Multimedia Systems Theresa Leonard 360-604-1478 ESS Technology Bill Windsor 510-492-1708 Euphonics, Inc.
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® Intel 810E2 Chipset Platform R Table 61. TV Encoders Vendors Component Contact Phone Chrontel CH7007 / CH7008 Chi Tai Hong (cthong@chrontel.com) (408)544-2150 Chrontel CH7010 / CH7011 Chi Tai Hong (cthong@chrontel.com) (408)544-2150 Conexant CN870 / CN871 Eileen Carlson (eileen.carlson@conexant.com) (858) 713-3203 Focus FS450 / FS451 Bill Schillhammer (billhammer@focusinfo.com) (978) 661-0146 Philips SAA7102A Marcus Rosin (marcus.rosin@philips.
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® Intel 810E2 Chipset Platform R This page is intentionally left blank.
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® Intel 810E2 Chipset Platform R Appendix A: Intel® 810E2 Chipset Platform Reference Schematics This appendix provides a set of schematics for Intel’s 810E2 chipset platform.
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A Clock Synthesizer INTEL® PENTIUM® III & INTEL® CELERON (TM) PROCESSOR (PGA370) / INTEL® 810E2 CHIPSET UNIPROCESSOR CUSTOMER REFERENCE SCHEMATICS REVISION 1.0 Title A Page Cover Sheet 1 Block Diagram 370-pin socket 2 AGTL Termination 5 Clock Synthesizer 82810e 6 7, 8, 9 Display Cache 10 System Memory 11, 12 ICH2 13, 14 FWH & UDAM 100 IDE1-2 15 Super I/O 16 17, 18 PCI Connectors 19 AC97 CODEC 20 Audio I/O 21 WOL, WOR & 2S1P 22 Kybrd / Mse / F.
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A Block Diagram 370-PIN SOCKET PROCESSOR VRM Clock DATA CTRL ADDR Term GTL BUS DATA CTRL ADDR Display Cache Memory 2 DIMM Modules GMCHE Digital Video Out Device IDE Primary USB Port 1-4 AUDIO CODEC A LPC Bus CNR CONNECTOR USB PCI CONN 4 PCI ADDR/DATA PCI CONN 3 PCI CNTRL ICH2 A PCI CONN 2 PCI CONN 1 UltraDMA/100 IDE Secondary AC'97 Link SIO FirmWare Hub Game Port Keyboard Mouse Floppy Serial 1 Serial 2 Parallel Title: REV.
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A VCCVID HA#[31:3] RS#0 RS#1 RS#2 AH26 AH22 AK28 RS#0 RS#1 RS#2 Socket 370_9 370 - Pin Socket Part 1 AK8 AH12 AH8 AN9 AL15 AH10 AL9 AH6 AK10 AN5 AL7 AK14 AL5 AN7 AE1 Z6 AG3 AC3 AJ1 AE3 AB6 AB4 AF6 Y3 AA1 AK6 Z4 AA3 AD4 X6 AC1 W3 AF4 HA#3 HA#4 HA#5 HA#6 HA#7 HA#8 HA#9 HA#10 HA#11 HA#12 HA#13 HA#14 HA#15 HA#16 HA#17 HA#18 HA#19 HA#20 HA#21 HA#22 HA#23 HA#24 HA#25 HA#26 HA#27 HA#28 HA#29 HA#30 HA#31 HA#32 HA#33 HA#34 HA#35 5,7 HD#[63:0] 5,7 HA#3 HA#4 HA#5 HA#6 HA#7 HA#8 HA#9 HA#10 HA#11 HA#12 HA#13
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1 VCMOS Decouping VTT1_5 Place 0603 Paclage near VCMOS Processor Pin VCMOS 14 AH14 AN17 AN25 AN19 AK20 AN27 AL23 AL25 AL27 AN31 AE37 BNR# BPRI# HTRDY# DEFER# HLOCK# DRDY# HITM# HIT# DBSY# HADS# 5,7 5,7 5,7 5,7 5,7 5,7 5,7 5,7 5,7 7 AJ33 AJ31 AK30 BSEL#0 BSEL#1 31 31 AN29 AL31 AL29 AH28 BR0# VTIN2 THRMDN 5 16,28 16,28 AE33 AG35 AH30 AJ35 M36 L37 AG33 AC35 AG37 AE35 A20M# STPCLK# CPUSLP# SMI# INTR NMI INIT# FERR# IGNNE# 13 13 13 13 13 13 13,15 13,32 13 VCC2_5 1K 330 DBRESET# 6 R15 ITPCL
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5 4 VTT1_5 VTT1_5 RN1 1 3 5 7 D C B 3 VTT1_5 RN2 2 4 6 8 1 3 5 7 HA#19 HA#21 HA#25 HA#10 1 3 5 7 56/8P4R RN6 2 4 6 8 HA#13 HA#16 HA#3 HA#9 1 3 5 7 56/8P4R RN10 2 4 6 8 RN4 HD#15 HD#1 HD#0 HD#6 1 3 5 7 HD#8 HD#5 HD#9 HD#4 1 3 5 7 56/8P4R RN7 2 4 6 8 HD#23 HD#21 HD#16 HD#24 1 3 5 7 56/8P4R RN11 2 4 6 8 HD#50 HD#53 HD#58 HD#46 56/8P4R RN14 2 4 6 8 HD#3 HD#12 HD#10 HD#17 1 3 5 7 56/8P4R RN15 2 4 6 8 HD#54 HD#55 HD#57 HD#63 2 4 6 8 2 4 6 8 HD#59 HD#48 HD#52 HD#40 1 3 5 7 HD#56
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A Clock Synthesizer VCC3_3 L2A 1 USBV3 22UF VCC3_3 2 1 + C5A 2 C4A 0.1UF VCC3_3 L3A L4A 0.1UF C13A C14A C15A C16A C6A C17A .001UF 0.1UF .001UF .1UF .001UF .001UF C18A .1UF C8A C7A .001UF C9A 0.1UF C19A C10A .001UF 22UF 0.1UF 1 1 C12A 2 22UF + C11A 2 MEMV3 PCIV3 - Place all decoupling caps as close to VCC/GND pins as possible - PCI_0/ICH pin has to go to the ICH. (This clock cannot be turned off through SMBus) - CPU_ITP pin must go to the ITP.
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A 82810E, PART 1: HOST INTERFACE VCC1_8 W13 X0 R57A 150 1% C27A 0.1UF F8 F10 F14 F7 VCC_CORE[13] VCC_CORE[12] VCC_CORE[11] F17 V7 V8 V9 V10 V14 F16 VCC_CORE[9] VCC_CORE[8] VCC_CORE[7] VCC_CORE[6] VCC_CORE[5] VCC_CORE[4] V15 V16 GTLREFA VCC_CORE[10] M5 VCC_CORE[3] GMCHGTLREF GTLREF VCC_CORE[2] V17 R56A 4 VCC_CORE[1] VCC_CORE[0] P6 U18 VCC1_8[2] VCC1_8[0] U3A R55A 75 1% VCC1_8[1] B20 VTT1_5 HD1# HD2# HD3# HD4# GTLREFB HD5# C28A .
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A 82810E, PART 2: SYSTEM MEMORY AND HUB INTERFACE VCC1_8 VCC3_3 VCC3_3SBY RP1A D7 SM_MAA4 1 8 B8 SM_MAA5 SM_MAA6 2 7 A8 3 6 B7 SM_MAA7 4 5 A7 SM_MAA8 D6 10 SM_MAA9 C6 SM_MAA10 SM_MAA11 D5 A5 J18 F18 G21 R18 VCC3_3[15] VCC3_3[14] VCC3_3[13] L21 VCC3_3[11] VCC3_3[12] B2 K6 F6 VCC3_3[9] F9 F15 G3 L3 C15 C7 SMAA1 VCC3_3[10] VCC3_3[8] VCC3_3[7] VCC3_3[6] VCC3_3[5] A9 VCC3_3[4] E7 SM_MAA2 SM_MAA3 VCC3_3[3] SM_MAA1 SMAA0 VCC3_3[2] C9 VCC3_3[0] SM_MAA0
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A 82810E, PART 3: DISPLAY CACHE VCC1_8 VCC1_8 L7A AND VIDEO INTERFACE FREQSEL 6,31 DC_DQM0 P21 DC_DQM1 R23 DC_DQM2 C23 DC_DQM3 F20 LTVDATA0 LDQM0 LTVDATA1 LDQM1 LTVDATA2 LDQM2 LTVDATA3 LDQM3 LTVDATA4 R_REFCLK 31 5 10 DC_WE# J19 10 DC_MA[11:0] 4 DC_MD31 M20 DC_MD29 DC_MA10 DC_MA11 DC_MD0 DC_MD1 M22 DC_MD2 L23 DC_MD3 L22 10 DC_MD[31:0] Comment IN = XOR Tree IN = Tri-state Mode *OUT = Normal Reads System Bus Freq.
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A 4MB Display Cache 32 DC_MA10 DC_MA11 20 19 A10 A11 DQ10 DQ11 DQ12 35 DC_CLK DC_CKE 34 DQ13 CLK DQ14 CKE DQ15 9 DC_CS# 18 9 9 DC_RAS# DC_CAS# 17 9 DC_WE# 15 16 DC_MD6 12 DC_MD8 40 DC_MD9 DC_MD11 45 DC_MD12 UDQM CAS# LDQM DC_MA9 32 DC_MA10 20 DC_MA11 19 DC_CLK 35 DC_CKE 34 DC_CS# 18 DC_RAS# 17 DC_MD13 48 DC_MD14 49 DC_MD15 36 DC_DQM1 14 DC_DQM0 44 38 13 7 DQ3 A4 DQ4 A5 A6 A7 A8 A9 A10 A11 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 CLK DQ13 CKE DQ14
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A SM_CKE1 SM_CKE0 SM_CS#1 SM_CS#0 SM_DQM7 SAO_PU 164 146 145 135 134 109 108 80 62 61 51 50 48 44 31 25 24 81 167 166 165 147 83 82 63 128 115 111 27 129 45 114 30 131 NC17 NC16 NC15 NC14 NC13 NC12 NC11 NC10 NC9 NC8 NC7 NC6 NC5 NC4 NC3 NC2 NC1 WP SA2 SA1 SA0 REGE SMBCLK SMBDATA CKE1 CKE0 RAS# CAS# WE# S3# S2# S1# S0# DQMB7 DQMB6 DQMB5 VCC6 130 VCC7 SM_DQM6 DQMB4 DQMB3 DQMB2 DQMB1 DQMB0 BA1 BA0 A13 A12 A11 A10 A9 A8
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38 123 SM_MAA11 39 28 29 46 47 112 113 130 131 SM_BS1 SM_DQM0 SM_DQM1 SM_DQM2 SM_DQM3 SM_DQM4 SM_DQM5 SM_DQM6 SM_DQM7 6,11 MEMCLK[7:0] A 129 SM_CS#3 63 SM_CKE1 SAO_PU intel R 164 146 145 135 134 109 108 80 62 61 51 50 48 44 31 25 24 81 167 166 165 147 83 82 128 SM_CKE0 115 111 27 45 SM_CS#2 114 NC17 NC16 NC15 NC14 NC13 NC12 NC11 NC10 NC9 NC8 NC7 NC6 NC5 NC4 NC3 NC2 NC1 WP SA2 SA1 SA0 REGE SMBCLK SMBDATA CKE1 CKE0 RAS# CAS# WE# S3# S2#
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A 17,18 17,18 17,18 17,18 A C39 10PF NPOP C_BE#0 C_BE#1 C_BE#2 C_BE#3 6 PCLK_0/ICH 17,18,32 FRAME# 17,18,32 DEVSEL# 17,18,32 IRDY# 17,18,32 TRDY# 17,18,32 STOP# 32 ICHRST# 17,18,32 PLOCK# 17,18 PAR 17,18,32 SERR# 17,18,32 PERR# 17,18,22 PCI_PME# 32 32 32 32 32 15 15 32 26 16,32 15 32 32 AA3 AB6 Y8 AA9 W11 V3 AB7 W8 V4 W1 AA15 AA7 W2 W7 Y7 Y15 PCI_REQ#A M3 L2 ICH_IRQ#E ICH_IRQ#F ICH_IRQ#G ICH_IRQ#H P66DET S66DET GPI8 EXTSMI# LPC_PME# N3 N2 N1 M4 Y11 AA11 Y14 W14 AB15 A15 D14 C14 L1 B14 A14 AB14 AA
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A B C V3SB 6 D E VCCRTC ICH_CLK14 ICH_CLK14 VCMOS 4 D1 SS12/SMD VCC5SBY R68 R69 1K VCC5 1K VCC3_3 R70 JP6 1 2 3 15K C42 R71 SS12/SMD R72 16 22,32 16,27 PWRBTN# ICH_RI# RSMRST# 1K W15 V21 AA13 W16 AB18 R20 Y16 W21 AA17 R21 Y17 AA18 AA16 AB16 AB17 T19 C43 6,16 6 O.
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8 7 6 5 4 3 VCC3_3 VCC3_3 14 PDD[0..15] 14 PDA[0..2] 32 BC27 R79 BC28 BC29 BC30 0.1UF 0.1UF 0.1UF IDERST# PDD[0..15] PDA[0..2] R78 PDD7 PDD6 PDD5 PDD4 PDD3 PDD2 PDD1 PDD0 IDERST# VCC3_3 0.1UF 0 R80 4.7K IDE1 33 U8 7,16,24,32 13 PCIRST# R81 8.
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8 7 6 11,12,14,25,26,32 SMBDATA D 4 3 2 -5VIN -12VIN +12VIN +3.3VIN VTT VCORE HM_VREF VTIN3 FB1 VCC5 1 IOAVCC 2 BC31 0.1UF THRMDN VCCRTC 0.
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A B C D E V3SB V3SB VCC3_3 VCC3_3 VCC5 VCC3_3 VCC5 VCC3_3 VCC5 VCC12- VCC5 VCC12- VCC12 VCC12 4 4 PCI1 18,32 18,32 PIRQ#B PIRQ#D 6 PCLK_1 13,32 PREQ#0 AD31 AD29 3 AD27 AD25 C_BE#3 AD23 AD21 AD19 AD17 C_BE#2 13,18,32 IRDY# 13,18,32 DEVSEL# 13,18,32 13,18,32 PLOCK# PERR# 13,18,32 SERR# PERR# C_BE#1 AD14 2 AD12 AD10 AD8 AD7 AD5 AD3 AD1 18,32 ACK64# ACK64# B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32
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A B C D V3SB VCC3_3 VCC3_3 VCC5 V3SB VCC3_3 VCC3_3 VCC5 VCC12- E VCC5 VCC12 VCC5 VCC12- VCC12 4 4 PCI3 17,32 17,32 PIRQ#D PIRQ#B 6 PCLK_3 13,32 PREQ#2 AD31 AD29 3 AD27 AD25 C_BE#3 AD23 AD21 AD19 AD17 C_BE#2 13,17,32 IRDY# 13,17,32 DEVSEL# 13,17,32 13,17,32 PLOCK# PERR# 13,17,32 SERR# PERR# C_BE#1 AD14 2 AD12 AD10 AD8 AD7 AD5 AD3 AD1 17,32 ACK64# ACK64# B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B3
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8 7 6 5 4 3 2 1 VCC5DUAL F1 14 FUSE_1.0A USBOC#0-1 USB1 1 FB3 + EC1 D 2 BEAD BC37 470PF 100UF 1 1 14 14 14 14 1 2 3 4 5 6 7 8 2 FB4 2 BEAD VCC0 DATA0DATA0+ GND0 VCC1 DATA1DATA1+ GND1 D USB_CON2 USBP0N USBP0P USBP1N USBP1P 1 1 2 FB6 BEAD BEAD BEAD 2 4 6 8 1 3 5 7 2 4 6 8 FB7 2 FB5 CP3 2 4 6 8 1 3 5 7 RN32 15K/8P4R 47PF/8P4C 1 3 5 7 V3SB C C R97 330K 26 CNR_OC# R98 X0 VCC5DUAL F2 14 FUSE_1.
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A VCC5 VCC5_AUDIO 1 VCC3_3 PFB1 2 BEAD 40 44 43 25 26 AVSS1 AVDD1 42 AVSS2 AVDD2 DVSS2 NC40 NC44 NC43 46 45 48 47 PRI_DWN_RST# AC_SDOUT AC_SDIN0 AC_SYNC AC_BITCLK 31 14,26,31 14,26,32 14,26 14,26 EAPD 21 C50 XTL_IN XTL_OUT A R100 CS4299 3 1K 2 VREF VREFOUT 10PF 28 29 AFILT1 A 11 5 8 10 6 CS1 CS0 CHAIN_CLK EAPD 27 X1UF CX3D MC5 RX3D 10K 34 R99 33 AC97SPKR LNLVL_OUT_R LNLVL_OUT_L U10 RESET# SDATA_OUT SDATA_IN SYNC BIT_CLK AC'97 CODEC FILT_R 26 21 21 DVDD2 DV
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8 7 6 5 4 3 2 1 Stereo HP/Spkr out R104 + C55 FB13 2 1 JK1 20 C56 R105 BEAD + 100UF 20 100UF 20 MC13 R106 1UF 20K FB14 2 1 D D BEAD PHONEJACK LNLVL_OUT_L C59 C57 C58 100PF 100PF 100PF R107 20K VCC5_AUDIO U11 20 MC14 R109 1UF 20K 1 2 3 4 LNLVL_OUT_R OUTA INA BYPASS GND R108 20K 8 7 6 5 VDD OUTB INB SHUTDN C60 100PF LM4880 MC15 1UF BC43 C C 0.
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A B C D VCC12- WAKE ON LAN VCC12 E VCC5 COM1 VCC5SBY COM1 D5 SS12/SMD PCI_PME# Q1 3 2 1 R120 100 HEADER_3*1(2MM) 2N3904 R121 4.7K 16 16 16 16 16 16 16 16 12 13 14 15 16 17 18 19 DCD#0 DTR#0 CTS#0 TXD0 RTS#0 RXD0 DSR#0 RI#0 -12V GND 12V 5V RY5 DA3 RY4 DA2 DA1 RY3 RY2 RY1 RA5 DY3 RA4 DY2 DY1 RA3 RA2 RA1 1 20 9 8 7 6 5 4 3 2 DCD0 DTR0 CTS0 TXDD0 RTS0 RXDD0 DSR0 RI0 2 4 6 8 13,17,18 WOL1 1 6 2 7 3 8 4 9 5 CN1 2 4 6 8 10 11 4 DCD0 DSR0 RXDD0 RTS0 TXDD0 BC44 CTS0 .
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A B C VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 D E VCC5 R126 0 XFUSE_1.0A 2 F3 FB18 R128 4.7K 4.7K R129 4.7K 4 R130 4.7K R131 4.7K R132 4.7K BEAD C70 4 1 R127 470PF J4 R133 R134 47 1K/8P4R 7 5 3 1 C72 22PF 8 6 4 2 C71 1000PF RN35 8 6 4 2 47 C74 1000PF C75 22PF C78 22PF C79 1000PF C80 22PF C81 1000PF VCC5DUAL C77 470PF 470PF 470PF/8P4C R135 R136 CN5 CN6 7 5 3 1 470PF/8P4C XFUSE_1.0A BEAD XFUSE_1.
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A Digital Video Out VCC3_3 VCC3_3 L8A L9A FPP1V3 + C89A 1 2 10UF 100PF 100PF 100PF 1 C90A C88A C87A FPDV3 1 2 10UF C86A 100PF 100PF + VCC3_3 2 C84A 1 C85A 2 L10A FPAV3 C91A 100PF 100PF R137A 10UF 1 2 C92A C93A 1 + 2 VCC1_8 1K R138A 400 1% 40 41 42 43 44 45 46 47 FTD[11:0] FTD11 FTD10 50 FTD9 FTD8 52 FTD7 54 FTD6 FTD5 55 FTD4 FTD3 59 FTD2 61 FTD1 FTD0 62 51 53 58 60 63 EXTRS_PU 12 33 1 VCC0 VCC1 49 23 29 18 VCC2 PVCC0 PVCC1 AVCC0 D23
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A Video Connectors VCC5 VGA Connector VCC1_8 CR1A 2 20 Pin Flat Panel Connector F6A 2 1 3 13 4 14 5 15 TX0+ 24 6 16 TX0- 7 17 - 1N5821 Place R66A,R67A,& R69A Close to VGA Connector Protection Circuit + R146A 75 1% for 20V Tolerance R144A 1K 2 24 C97A 24 TX2- 3.3PF TX2+ 12 C96A 11 2 BLM11B750S 3.
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8 7 6 V3SB 5 VCC5SBY 4 VCC5 3 2 VCC3_3 VCC12-VCC5SBY 1 VCC12V3SB VCC5 CNRSLOT1 R161 10K R162 R163 220 10K R164 150 R160 2.2K R165 220 D 13 13 PN1 16 13 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 KEYLOCK# EXTSMI# PANSWIN R168 10K BC47 R169 0 0.
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A B C VCC3_3 D VCC5SBY E VCC5 V3SB ATXPR1 PS_ON VCC_54 VCC5 3.3V -12V GND PS_ON GND GND GND -5V +5V +5V 1 2 3 4 5 6 7 8 9 10 3.3V 3.3V GND +5V GND +5V GND PWROK AUX5V +12V BC49 .1U D10 1N4148 R181 15K VCC5SBY 14 16 11 12 13 14 15 16 17 18 19 20 U19A 14 1 VCC5SBY 7 VCC12 ATXPWROK 2 1 4.
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A B C D E 4 4 JP10 VTIN3 16 HM_VREF 16 VTIN1 4,16 VTIN2 PR8 VCC12 VCC5 RT1 10K,1% X10K_1%-THRM/0603 R189 4.7K R190 CHASSIS FAN Q7 2N2907 +12CHFAN 1K D11 1N4148 Q8 2N7002 16 FANPWM1 R193 EC3 + 22UF 510 C120 1K FAN1 3 2 1 FANIO1 4,16 PR10 VCC12 Q9 2N2907 +12CPUFAN D12 R197 1N4148 16 FANPWM2 R200 510 EC4 + 22UF FANIO2 14,16 VTT1_5 10K R198 VCC3_3 10K R199 16 PR12 56K,1% HEADER_3 R201 R195 1K FAN2 3 2 1 VCC12 VCCRTC VCCVID CPU FAN 4.
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A B C VCC12 D VCC3_3 E VCC5 4 4 14 R205 VRM_PWRGD R203 R204 10 1K L15 1UH 33 VCCPWM C121 + EC6 + 1500UF 1500UF 1500UF 1500UF EC7 + EC8 + C122 VDDQ 3 R207 9 4.7K R208 1 10 L16 EC9 + 2 7UH C123 8 VCC Q11 HUF76107D3S TO-252 U22 PGOOD C124 1000PF 28 1UF OCSET2 D14 1N5820 UGATE2 UGATE1 PHASE2 PHASE1 LGATE1 10 11 VSEN2 SELECT PGND VCC3_3 VSEN1 FB1 Q14 HUF75307D3S TO-252 18 19 VCC3_3 23 COMP1 15 EC21 + 14 100UF 25 VSEN4 HIP6020 R210 5.
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A B C VCC5SBY VCC12 D VCC3_3 E VCC5 VCC2_5 4 0.
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A B C D E VCC3_3 4 4 R224 8.2K R_REFCLK 9 FREQSEL FMOD1 ICH_SPKR 6,9 6 14,26 R222 1.8K R221 1.8K 4 4 SW2 1 2 3 4 5 6 7 8 BSEL#0 BSEL#1 3 26 PRI_DWN 14,26 AC_RST# DIPSW-8 16 15 14 13 12 11 10 9 JUMPER JP? R223 10K R225 8.
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B C ICH VCC5 4 R1 R2 R3 R4 R5 R6 R7 R8 C C 2.7K/10P8R RN39 2 4 6 8 13,18 13,17 13,17 PREQ#2 PREQ#1 PREQ#0 1 3 5 7 13,18 13 13 17,18 PREQ#3 PREQ#5 PREQ#4 ACK64# 1 3 5 7 2.7K/8P4R RN41 2 4 6 8 1 3 5 7 2.7K/8P4R RN43 2 4 6 8 17 17 18 18 REQ64#1 REQ64#2 REQ64#3 REQ64#4 1 3 5 7 4.7K/8P4R RN38 2 4 6 8 V3SB 1 3 5 7 1 3 5 7 4.7K/8P4R RN40 2 4 6 8 V3SB GPI8 GPIO25 GPIO27 GPIO28 PCI_REQ#A OVT# KBRST# A20GATE 1 3 5 7 8.2K/8P4R RN42 2 4 6 8 VCC3_3 13 14,16 13,16 13,16 8.
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A UNUSED GATES VCC3_3SBY VCC3_3SBY O 14 SN74LVC06A 3 74LVC14A 14 2 U21D 7 O GND A GND 1 SN74LVC08A 6 2 7 A U26B 14 VCC 1 U26A 1 2 5 U27A U21C 14 VCC 14 U25A 7 VCC3_3SBY 14 VCC3_3 74LVC14A 4 6 7 9 8 5 14 VCC 4 14 4 SN74LVC06A 14 Y 74LS132 14 4 7 9 SN74LVC06A U28C 14 5 6 10 A Y 8 B 74LS132 7 7 U20C VCC 6 SN74LVC07A GND SN74LVC07A O A B 7 14 VCC 3 A 6 14 7 6 U20B A U28B 14 VCC 7 5 U25C U27C O GND A 4 SN74LVC07A 5 5 2 7
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A B C VCC12 VCC3_3 " ATX POWER " " ATX POWER " VCC5 " ATX POWER " BC61 BC62 EC38 BC63 BC64 EC39 BC65 0.1UF 0.1UF 22UF 0.1UF 0.1UF 0.1UF 22UF BC53 BC54 BC55 BC56 EC36 BC57 BC58 BC59 BC60 0.1UF 0.1UF 0.1UF 0.1UF 22UF 0.1UF 0.1UF 0.1UF 0.1UF BC66 22UF 22UF E VCC_5- " ATX POWER " EC35 EC37 D VCC12- " ATX POWER " 0.1UF 4 4 VCCVID MC24 4.7UF VDDQ MC25 MC26 4.7UF MC27 4.7UF 4.7UF MC28 MC29 4.7UF MC30 4.7UF 4.7UF MC31 4.7UF MC32 4.