User`s manual

Using the Verilog PLI
5-92 Verilog Simulation ModelSim Xilinx User’s Manual
Verilog-XL compatible routines
The following PLI routines are not define in the IEE Std 1364, but ModelSim
Verilog provides them for compatibility with Verilog-XL.
char *acc_decompile_exp(handle condition)
This routine provides similar functionality to the Verilog-XL
acc_decompile_expr routine. The condition argument must be a handle obtained
from the acc_handle_condition routine. The value returned by
acc_decompile_exp is the string representation of the condition expression.
char *tf_dumpfilename(void)
This routine returns the name of the VCD file.
void tf_dumpflush(void)
A call to this routine flushes the VCD file buffer (same effect as calling
$dumpflush in the Verilog code).
int tf_getlongsimtime(int *aof_hightime)
tf_real_to_long tf_rosynchronize tf_irosynchronize
tf_scale_longdelay tf_scale_realdelay tf_setdelay
tf_isetdelay tf_setlongdelay tf_isetlongdelay
tf_setrealdelay tf_isetrealdelay tf_setworkarea
tf_isetworkarea tf_sizep tf_isizep
tf_spname tf_ispname tf_strdelputp
tf_istrdelputp tf_strgetp tf_istrgetp
tf_strgettime tf_strlongdelputp tf_istrlongdelputp
tf_strrealdelputp tf_istrrealdelputp tf_subtract_long
tf_synchronize tf_isynchronize tf_testpvc_flag
tf_itestpvc_flag tf_text tf_typep
tf_itypep tf_unscale_longdelay tf_unscale_realdelay
tf_warning tf_write_save