User`s manual

Using the Verilog PLI
ModelSim Xilinx User’s Manual Verilog Simulation 5-91
IEEE Std 1364 TF routines
ModelSim Verilog supports the following TF routines, described in detail in the
IEEE Std 1364.
io_mcdprintf io_printf mc_scan_plusargs
tf_add_long tf_asynchoff tf_iasynchoff
tf_asynchon tf_iasynchon tf_clearalldelays
tf_iclearalldelays tf_compare_long tf_copypvc_flag
tf_icopypvc_flag tf_divide_long tf_dofinish
tf_dostop tf_error tf_evaluatep
tf_ievaluatep tf_exprinfo tf_iexprinfo
tf_getcstringp tf_igetcstringp tf_getinstance
tf_getlongp tf_igetlongp tf_getlongtime
tf_igetlongtime tf_getnextlongtime tf_getp
tf_igetp tf_getpchange tf_igetpchange
tf_getrealp tf_igetrealp tf_getrealtime
tf_igetrealtime tf_gettime tf_igettime
tf_gettimeprecision tf_igettimeprecision tf_gettimeunit
tf_igettimeunit tf_getworkarea tf_igetworkarea
tf_long_to_real tf_longtime_tostr tf_message
tf_mipname tf_imipname tf_movepvc_flag
tf_imovepvc_flag tf_multiply_long tf_nodeinfo
tf_inodeinfo tf_nump tf_inump
tf_propagatep tf_ipropagatep tf_putlongp
tf_iputlongp tf_putp tf_iputp
tf_putrealp tf_iputrealp tf_read_restart