User`s manual

Using the Verilog PLI
ModelSim Xilinx User’s Manual Verilog Simulation 5-89
The type and fulltype constants for VHDL objects are defined in the acc_vhdl.h
include file. All of these objects (except signals) are scope objects that define
levels of hierarchy in the Structure window. Currently, the PLI ACC interface has
no provision for obtaining handles to generics, types, constants, attributes,
subprograms, and processes.
IEEE Std 1364 ACC routines
ModelSim Verilog supports the following ACC routines, described in detail in the
IEEE Std 1364
accBlock accBlock block statement
accForLoop accForLoop for loop statement
accForeign accShadow foreign scope created by mti_CreateRegion( )
accGenerate accGenerate generate statement
accPackage accPackage package declaration
accSignal accSignal signal declaration
acc_append_delays acc_append_pulsere acc_close
acc_collect acc_compare_handles acc_configure
acc_count acc_fetch_argc acc_fetch_argv
acc_fetch_attribute acc_fetch_attribute_int acc_fetch_attribute_str
acc_fetch_defname acc_fetch_delay_mode acc_fetch_delays
acc_fetch_direction acc_fetch_edge acc_fetch_fullname
acc_fetch_fulltype acc_fetch_index acc_fetch_location
acc_fetch_name acc_fetch_paramtype acc_fetch_paramval
acc_fetch_polarity acc_fetch_precision acc_fetch_pulsere
acc_fetch_range acc_fetch_size acc_fetch_tfarg
Type Fulltype Description